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RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , 20191214- December 2019

15 “L” Standard Extension for Decimal Floating-Point, Version 0.0

This chapter is a draft proposal that has not been ratified by the Foundation.

This chapter is a placeholder for the specification of a standard extension named “L” designed to support decimal floating-point arithmetic as defined in the IEEE 754-2008 standard.

15.1 Decimal Floating-Point Registers

Existing floating-point registers are used to hold 64-bit and 128-bit decimal floating-point values, and the existing floating-point load and store instructions are used to move values to and from memory.

Due to the large opcode space required by the fused multiply-add instructions, the decimal floating-point instruction extension will require five 25-bit major opcodes in a 30-bit encoding space.