Contributors include: Alon Amid, Krste Asanovic, Allen Baum, Alex Bradbury, Tony Brewer, Chris Celio, Aliaksei Chapyzhenka, Silviu Chiricescu, Ken Dockser, Bob Dreyer, Roger Espasa, Sean Halle, John Hauser, David Horner, Bruce Hoult, Bill Huffman, Nicholas Knight, Constantine Korikov, Ben Korpan, Hanna Kruppe, Yunsup Lee, Guy Lemieux, Grigorios Magklis, Filip Moc, Rich Newell, Albert Ou, David Patterson, Colin Schmidt, Alex Solomatnikov, Steve Wallach, Andrew Waterman, Jim Wilson.
Known issues with current version:

encoding needs better formatting

vector memory consistency model needs to be clarified

interaction with privileged architectures
Changes from v0.9
SLEN=VLEN layout mandatory
The group has decided to make the SLEN=VLEN layout mandatory. Inregister layout of the bytes of a vector matches inmemory layout of bytes in a vector. Many of the optimizations possible with the earlier SLEN<VLEN layouts can be achieved with microarchitectural techniques on wide datapath machines, and SLEN=VLEN provides a much simpler specification and interface to software.
Support ELEN > VLEN for LMUL > 1
Specification was loosened to allow elements wider than a single vector register to be supported using a vector register group, but profiles can still mandate a minimum ELEN when LMUL = 1.
Defined vector FP exception behavior
Defined interaction of misa.v
and mstatus.vs
Defined integer narrowing pseudoinstruction vncvt.x.x.v vd,vs,vm
Added reciprocal and reciprocal squareroot estimate instructions
Added EEW encoding to whole register moves and load/stores to support microarchitectures with internal data rearrangement.
Added vrgatherei16
instruction
Rearranged bits in vtype
to make vlmul
bits into a contiguous field
Moved EDIV to appendix and removed instruction encoding for dot instructions to make clear not part of v1.0
Moved quadwidening mulacc to appendix and removed instruction encodings to make clear not part of v1.0
1. Introduction
This document describes the draft of version 1.0 of the RISCV vector extension.
Note

This is a draft of the stable proposal for the vector extension specification to be used for implementation and evaluation. Once the draft label is removed, version 1.0 is intended to be sent out for public review as part of the RISCV International ratification process. Version 1.0 is also considered stable enough to begin developing toolchains, functional simulators, and initial implementations, including in upstream software projects, and is not expected to have major functionality changes except if serious issues are discovered during ratification. Once ratified, the spec will be given version 2.0. 
This draft spec is intended to capture how the complete set of currently defined vector instructions, but is not intended to determine what set of vector instructions and which supported element widths are mandatory for a given platform profile.
The term base vector extension is used informally to describe the standard set of vector ISA components that will be required for the singleletter "V" extension, which is intended for use in standard server and applicationprocessor platform profiles. The set of mandatory instructions and supported element widths will vary with the base ISA (RV32I, RV64I) as described below.
Other profiles, including embedded profiles, may choose to mandate only subsets of these extensions. The exact set of mandatory supported instructions for an implementation to be compliant with a given profile will only be determined when each profile spec is ratified. For convenience in defining subset profiles, vector instruction subsets are given ISA string names beginning with the "Zv" prefix.
The document describes all the individual features to be included in the base vector extension.
Note

The set of instructions to be included or not in the base "V" extension, and the naming of all the vector instruction subsets and extensions is still under review in this draft. 
The base vector extension is designed to act as a base for additional vector extensions in various domains, including cryptography and machine learning.
2. Implementationdefined Constant Parameters
Each hart supporting the vector extension defines two parameters:

The maximum size of a vector element that any operation can produce or consume in bits, ELEN ≥ 8, which must be a power of 2.

The number of bits in a single vector register, VLEN, which must be a power of 2.
Note

Profiles may set further constraints on these parameters, for example, requiring that ELEN ≥ max(XLEN,FLEN), or requiring a minimum VLEN value. 
The ISA supports writing binary code that under certain constraints will execute portably on harts with different values for these parameters.
Note

Code can be written that will expose differences in implementation parameters. 
Note

Thread contexts with active vector state cannot be migrated during execution between harts that have any difference in VLEN or ELEN parameters. 
3. Vector Extension Programmer’s Model
The vector extension adds 32 vector registers, and seven unprivileged
CSRs (vstart
, vxsat
, vxrm
, vcsr
, vtype
, vl
, vlenb
) to a
base scalar RISCV ISA.
Address  Privilege  Name  Description 

0x008 
URW 
vstart 
Vector start position 
0x009 
URW 
vxsat 
FixedPoint Saturate Flag 
0x00A 
URW 
vxrm 
FixedPoint Rounding Mode 
0x00F 
URW 
vcsr 
Vector control and status register 
0xC20 
URO 
vl 
Vector length 
0xC21 
URO 
vtype 
Vector data type register 
0xC22 
URO 
vlenb 
VLEN/8 (vector register length in bytes) 
3.1. Vector Registers
The vector extension adds 32 architectural vector registers,
v0
v31
to the base scalar RISCV ISA.
Each vector register has a fixed VLEN bits of state.
Note

Zfinx ("F in X") is a new ISA option under consideration where floatingpoint instructions take their arguments from the integer register file. The 0.9 vector extension is also compatible with this option. 
3.2. Vector Context Status in mstatus
A vector context status field, VS
, is added to mstatus[10:9]
and shadowed
in sstatus[10:9]
. It is defined analogously to the floatingpoint context
status field, FS
.
Attempts to execute any vector instruction, or to access the vector
CSRs, raise an illegalinstruction exception when the VS
field is
set to Off.
When the VS
field is set to Initial or Clean, executing any
instruction that changes vector state, including the vector CSRs, will
change VS
to Dirty.
Note

Implementations may also change VS field to Dirty at any time,
even when there is no change in vector state. Accurate setting of the
VS field is an optimization.

Implementations may have a writable misa.v
field. Analogous to the
way in which the floatingpoint unit is handled, the mstatus.vs
field may exist even if misa.v
is clear.
Note

Allowing mstatus.vs to exist when misa.v is clear, enables
vector emulation and simplifies handling of mstatus.vs in systems
with writable misa.v .

3.3. Vector type register, vtype
The readonly XLENwide vector type CSR, vtype
provides the
default type used to interpret the contents of the vector register
file, and can only be updated by vsetvl{i}
instructions. The vector
type also determines the organization of elements in each vector
register, and how multiple vector registers are grouped.
Note

Earlier drafts allowed the vtype register to be written using
regular CSR writes. Allowing updates only via the vsetvl{i}
instructions simplifies maintenance of the vtype register state.

In the base vector extension, the vtype
register has five fields,
vill
, vma
, vta
, vsew[2:0]
, and vlmul[2:0]
.
Bits  Name  Description 

XLEN1 
vill 
Illegal value if set 
XLEN2:8 
Reserved (write 0) 

7 
vma 
Vector mask agnostic 
6 
vta 
Vector tail agnostic 
5:3 
vsew[2:0] 
Selected element width (SEW) setting 
2:0 
vlmul[2:0] 
Vector register group multiplier (LMUL) setting 
Note

The smallest base implementation supporting ELEN=32 requires
storage for only seven bits of storage in vtype , two bits for ma
and ta , two bits for vsew[1:0] and three bits for vlmul[2:0] .
The illegal value represented by vill can be encoded using the
illegal 64bit combination in vsew[1:0] without requiring an
additional storage bit.

Note

Further standard and custom extensions to the vector base will extend these fields to support a greater variety of data types. 
Note

It is anticipated that an extended 64bit instruction encoding would allow these fields to be specified statically in the instruction encoding. 
3.3.1. Vector selected element width vsew[2:0]
The value in vsew
sets the dynamic selected element width
(SEW). By default, a vector register is viewed as being divided into
VLEN/SEW selectedwidth elements.
Note

In the base vector "V" extension, only SEW up to ELEN = max(XLEN,FLEN) are required to be supported. Other profiles may impose different constraints on ELEN. 
vsew[2:0]  SEW  

0 
0 
0 
8 
0 
0 
1 
16 
0 
1 
0 
32 
0 
1 
1 
64 
1 
0 
0 
128 
1 
0 
1 
256 
1 
1 
0 
512 
1 
1 
1 
1024 
SEW  Elements per vector register 

64 
2 
32 
4 
16 
8 
8 
16 
The supported element width may vary with LMUL, but profiles may mandate the minimum SEW that must be supported with LMUL=1.
Note

Some implementations may support larger SEWs only when bits from multiple vector registers are combined. The base V vector standard requires that SEW=max(XLEN,FLEN) is supported with LMUL=1. 
Note

Software that relies on large EEW should attempt to use the
largest LMUL, and hence the fewest vector register groups, to increase
the number of implementations on which the code will run. The vill
bit in vtype should be checked to see if the configuration is
supported, and an alternate code path provided if it is
not. Alternatively, a profile can mandate the minimum SEW at each LMUL
setting.

3.3.2. Vector Register Grouping (vlmul[2:0]
)
Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers. The term vector register group is used herein to refer to one or more vector registers used as a single operand to a vector instruction. Vector register groups allow doublewidth or larger elements to be operated on with the same vector length as selectedwidth elements. Vector register groups also provide greater execution efficiency for longer application vectors.
The vector length multiplier, LMUL, when greater than 1, represents the default number of vector registers that are combined to form a vector register group. LMUL can have integer values 1,2,4,8.
LMUL can also be a fractional value, reducing the number of bits used in a vector register. LMUL can have fractional values 1/2, 1/4, 1/8. Fractional LMUL is used to increase the number of usable architectural registers when operating on mixedwidth values, by not requiring that largerwidth vectors occupy multiple vector registers. Instead, wider values can occupy a single vector register and narrower values can occupy a fraction of a vector register.
Implementations must support fractional LMUL settings for LMUL ≥
SEW/ELEN, for the ELEN value at LMUL=1. An attempt to set an
unsupported SEW and LMUL configuration sets the vill
bit in vtype
.
Note

Requiring LMUL ≥ SEW/ELEN allows software operating on mixedwidth elements to only use a single vector register to hold the widest (ELEN) elements, with fractional LMUL used to hold narrower elements. When LMUL < SEW/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. 
The behavior of an implementation when LMUL < SEW/ELEN and the vill
bit is not set is reserved.
Note

Requiring all implementations to set vill in this case would
prohibit future use of this encoding in an extension, so to allow for
a future definition of LMUL<SEW/ELEN behavior, we consider the
behavior in this case when vill is not set to be reserved.

Note

It is recommended that assemblers provide a warning (not an
error) if a vsetvli instruction attempts to write an LMUL < SEW/ELEN.

LMUL is set by the signed vlmul
field in vtype
(LMUL =
2^{vlmul[2:0]}).
The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings as shown in the table below.
vlmul  LMUL  #groups  VLMAX  Registers grouped with register n  

1 
0 
0 
 
 
 
reserved 
1 
0 
1 
1/8 
32 
VLEN/SEW/8 

1 
1 
0 
1/4 
32 
VLEN/SEW/4 

1 
1 
1 
1/2 
32 
VLEN/SEW/2 

0 
0 
0 
1 
32 
VLEN/SEW 

0 
0 
1 
2 
16 
2*VLEN/SEW 

0 
1 
0 
4 
8 
4*VLEN/SEW 

0 
1 
1 
8 
4 
8*VLEN/SEW 

When LMUL=2, the vector register group contains vector register v
n and vector register v
n+1, providing twice the vector
length in bits. Instructions specifying a vector register group with
an oddnumbered vector register will raise an illegal instruction
exception.
When LMUL=4, the vector register group contains four vector registers, and instructions specifying vector register groups using vector register numbers that are not multiples of four will raise an illegal instruction exception.
When LMUL=8, the vector register group contains eight vector registers, and instructions specifying vector register groups using register numbers that are not multiples of eight will raise an illegal instruction exception.
Mask registers are always contained in a single vector register, regardless of LMUL.
3.3.3. Vector Tail Agnostic and Vector Mask Agnostic vta
and vma
These two bits modify the behavior of destination tail elements and destination inactive maskedoff elements respectively during the execution of vector instructions. The tail and inactive sets contain element positions that are not receiving new results during a vector operation, as defined in Section Prestart, Active, Inactive, Body, and Tail Element Definitions.
All systems must support all four options:
vta 
vma 
Tail Elements  Inactive Elements 

0 
0 
undisturbed 
undisturbed 
0 
1 
undisturbed 
agnostic 
1 
0 
agnostic 
undisturbed 
1 
1 
agnostic 
agnostic 
When a set is marked undisturbed, the corresponding set of destination elements in any vector or mask destination operand retain the value they previously held.
When a set is marked agnostic, the corresponding set of destination elements in any vector or mask destination operand can either retain the value they previously held, or are overwritten with 1s. Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.
Note

The agnostic policy was added to accommodate machines with vector register renaming, and/or that have deeply temporal vector registers. With an undisturbed policy, all elements would have to be read from the old physical destination vector register to be copied into the new physical destination vector register. This causes an inefficiency when these inactive or tail values are not required for subsequent calculations. 
Note

The intent is for software to select the option that reduces microarchitectural work by selecting agnostic when the value in the respective set does not matter. 
Note

The value of all 1s instead of all 0s was chosen for the overwrite value to discourage software developers from depending on the value written. 
Note

A simple inorder implementation can ignore the setting and
simply execute all vector instructions using the undisturbed
policy. The vta and vma state bits must still be provided in
vtype for compatibility and to support thread migration.

Note

An outoforder implementation can choose to implement tailagnostic + maskagnostic using tailagnostic + maskundisturbed to reduce implementation complexity. 
Note

The definition of agnostic result policy is left loose to accommodate migrating application threads between harts on a small inorder core (which probably leaves agnostic regions undisturbed) and harts on a larger outoforder core with register renaming (which probably overwrites agnostic elements with 1s). As it might be necessary to restart in the middle, we allow arbitrary mixing of agnostic policies within a single vector instruction. This allowed mixing of policies also enables implementations that might change policies for different granules of a vector register, for example, using undisturbed within a granule that is actively operated on but renaming to all 1s for granules in the tail. 
The assembly syntax adds two flags to the vsetvli
instruction:
ta # Tail agnostic tu # Tail undisturbed ma # Mask agnostic mu # Mask undisturbed vsetvli t0, a0, e32,m4,ta,ma # Tail agnostic, mask agnostic vsetvli t0, a0, e32,m4,tu,ma # Tail undisturbed, mask agnostic vsetvli t0, a0, e32,m4,ta,mu # Tail agnostic, mask undisturbed vsetvli t0, a0, e32,m4,tu,mu # Tail undisturbed, mask undisturbed
Note

To maintain backward compatibility in the short term and reduce
software churn in the move to 0.9, when these flags are not specified
on a vsetvli , they should default to
maskundisturbed/tailundisturbed. The use of vsetvli without these
flags should be deprecated, however, such that the specifying a flag
setting becomes mandatory. If anything, the default should be
tailagnostic/maskagnostic, so software has to specify when it cares
about the nonparticipating elements, but given the historical meaning
of the instruction prior to introduction of these flags, it is safest
to always require them in future assembly code.

3.3.4. Vector Type Illegal vill
The vill
bit is used to encode that a previous vsetvl{i}
instruction attempted to write an unsupported value to vtype
.
Note

The vill bit is held in bit XLEN1 of the CSR to support
checking for illegal values with a branch on the sign bit.

If the vill
bit is set, then any attempt to execute a vector instruction
that depends upon vtype
will raise an illegalinstruction exception.
Note

vsetvl{i} and wholeregister loads, stores, and moves do not depend
upon vtype .

When the vill
bit is set, the other XLEN1 bits in vtype
shall be
zero.
3.4. Vector Length Register vl
The XLENbitwide readonly vl
CSR can only be updated by the
vsetvli
and vsetvl
instructions, and the faultonlyfirst vector load
instruction variants.
The vl
register holds an unsigned integer specifying the number of
elements to be updated by a vector instruction. Elements in any
destination vector register group with indices ≥ vl
are unmodified during
execution of a vector instruction. When vstart
≥ vl
,
no elements are updated in any destination vector register group.
Note

As a consequence, when vl =0, no elements are updated in the
destination vector register group, regardless of vstart .

Note

Instructions that write a scalar integer or floatingpoint register
do so even when vstart ≥ vl .

Note

The number of bits implemented in vl depends on the
implementation’s maximum vector length of the smallest supported
type. The smallest vector implementation, RV32IV, would need at least
six bits in vl to hold the values 032 (with VLEN=32, LMUL=8 and
SEW=8 results in VLMAX of 32).

3.5. Vector Byte Length vlenb
The XLENbitwide readonly CSR vlenb
holds the value VLEN/8,
i.e., the vector register length in bytes.
Note

The value in vlenb is a designtime constant in any
implementation.

Note

Without this CSR, several instructions are needed to calculate
VLEN in bytes, and the code has to disturb current vl and vtype
settings which require them to be saved and restored.

3.6. Vector Start Index CSR vstart
The vstart
readwrite CSR specifies the index of the first element
to be executed by a vector instruction.
Normally, vstart
is only written by hardware on a trap on a vector
instruction, with the vstart
value representing the element on which
the trap was taken (either a synchronous exception or an asynchronous
interrupt), and at which execution should resume after a resumable
trap is handled.
All vector instructions are defined to begin execution with the
element number given in the vstart
CSR, leaving earlier elements in
the destination vector undisturbed, and to reset the vstart
CSR to
zero at the end of execution.
Note

All vector instructions, including vsetvl{i} , reset the vstart
CSR to zero.

vstart
is not modified by vector instructions that raise illegalinstruction
exceptions.
For instructions where the number of elements to be performed is set
by vl
, if the value in the vstart
register is greater than or
equal to the vector length vl
then no element operations are
performed. The vstart
register is then reset to zero.
The vstart
CSR is defined to have only enough writable bits to hold
the largest element index (one less than the maximum VLMAX) or
lg2(VLEN) bits. The upper bits of the vstart
CSR are hardwired to
zero (reads zero, writes ignored).
Note

The maximum vector length is obtained with the largest LMUL
setting (8) and the smallest SEW setting (8), so VLMAX_max = 8*VLEN/8
= VLEN. For example, for VLEN=256, vstart would have 8 bits to
represent indices from 0 through 255.

The vstart
CSR is writable by unprivileged code, but nonzero
vstart
values may cause vector instructions to run substantially
slower on some implementations, so vstart
should not be used by
application programmers. A few vector instructions cannot be
executed with a nonzero vstart
value and will raise an illegal
instruction exception as defined below.
Note

Making vstart visible to unprivileged code supports userlevel
threading libraries.

Implementations are permitted to raise illegal instruction exceptions when
attempting to execute a vector instruction with a value of vstart
that the
implementation can never produce when executing that same instruction with
the same vtype
setting.
Note

For example, some implementations will never take interrupts during
execution of a vector arithmetic instruction, instead waiting until the
instruction completes to take the interrupt. Such implementations are
permitted to raise an illegal instruction exception when attempting to execute
a vector arithmetic instruction when vstart is nonzero.

Note

When migrating a software thread between two harts with
different microarchitectures, the vstart value might not be
supported by the new hart microarchitecture. The runtime on the
receiving hart might then have to emulate instruction execution to a
supported vstart element position. Alternatively, migration events
can be constrained to only occur at mutually supported vstart
locations.

3.7. Vector FixedPoint Rounding Mode Register vxrm
The vector fixedpoint roundingmode register holds a twobit
readwrite roundingmode field. The vector fixedpoint roundingmode
is given a separate CSR address to allow independent access, but is
also reflected as a field in vcsr
.
The fixedpoint rounding algorithm is specified as follows.
Suppose the prerounding result is v
, and d
bits of that result are to be
rounded off.
Then the rounded result is (v >> d) + r
, where r
depends on the rounding
mode as specified in the following table.
Bits [1:0]  Abbreviation  Rounding Mode  Rounding increment, r 


0 
0 
rnu 
roundtonearestup (add +0.5 LSB) 

0 
1 
rne 
roundtonearesteven 

1 
0 
rdn 
rounddown (truncate) 

1 
1 
rod 
roundtoodd (OR bits into LSB, aka "jam") 

The rounding functions:
roundoff_unsigned(v, d) = (unsigned(v) >> d) + r roundoff_signed(v, d) = (signed(v) >> d) + r
are used to represent this operation in the instruction descriptions below.
Bits[XLEN1:2] should be written as zeros.
Note

The rounding mode can be set with a single csrwi instruction.

3.8. Vector FixedPoint Saturation Flag vxsat
The vxsat
CSR holds a single readwrite bit that indicates if a
fixedpoint instruction has had to saturate an output value to fit
into a destination format.
The vxsat
bit is mirrored in vcsr
.
3.9. Vector Control and Status Register vcsr
The vxrm
and vxsat
separate CSRs can also be accessed via fields
in the vector control and status CSR, vcsr
.
Bits  Name  Description 

2:1 
vxrm[1:0] 
Fixedpoint rounding mode 
0 
vxsat 
Fixedpoint accrued saturation flag 
3.10. State of Vector Extension at Reset
The vector extension must have a consistent state at reset. In
particular, vtype
and vl
must have values that can be read and
then restored with a single vsetvl
instruction.
Note

It is recommended that at reset, vtype.vill is set, the
remaining bits in vtype are zero, and vl is set to zero.

The vstart
, vxrm
, vxsat
CSRs can have arbitrary values at reset.
Note

Any use of the vector unit will require an initial vsetvl{i} ,
which will reset vstart . The vxrm and vxsat fields should be
reset explicitly in software before use.

The vector registers can have arbitrary values at reset.
4. Mapping of Vector Elements to Vector Register State
The following diagrams illustrate how different width elements are packed into the bytes of a vector register depending on the current SEW and LMUL settings, as well as implementation VLEN. Elements are packed into each vector register with the leastsignificant byte in the lowestnumbered bits.
4.1. Mapping for LMUL ≤ 1
When LMUL=1, elements are simply packed in order from the leastsignificant to mostsignificant bits of the vector register.
Note

To increase readability, vector register layouts are drawn with bytes ordered from right to left with increasing byte address. Bits within an element are numbered in a littleendian format with increasing bit index from right to left corresponding to increasing magnitude. 
LMUL=1 examples. The element index is given in hexadecimal and is shown placed at the leastsignificant byte of the stored element. VLEN=32b Byte 3 2 1 0 SEW=8b 3 2 1 0 SEW=16b 1 0 SEW=32b 0 VLEN=64b Byte 7 6 5 4 3 2 1 0 SEW=8b 7 6 5 4 3 2 1 0 SEW=16b 3 2 1 0 SEW=32b 1 0 SEW=64b 0 VLEN=128b Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b 7 6 5 4 3 2 1 0 SEW=32b 3 2 1 0 SEW=64b 1 0 SEW=128b 0 VLEN=256b Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=32b 7 6 5 4 3 2 1 0 SEW=64b 3 2 1 0 SEW=128b 1 0
When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector register are used. The remaining space in the vector register is treated as part of the tail.
Example, VLEN=128b, LMUL=1/4 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b             3 2 1 0 SEW=16b       1 0 SEW=32b    0
4.2. Mapping with LMUL > 1
When vector registers are grouped, the elements of the vector register group are striped across the constituent vector registers. The elements are packed contiguously in element order in each vector register in the group, moving to the next highestnumbered vector register in the group once each vector register is filled.
LMUL > 1 examples VLEN=32b, SEW=8b, LMUL=2 Byte 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4 VLEN=32b, SEW=16b, LMUL=2 Byte 3 2 1 0 v2*n 1 0 v2*n+1 3 2 VLEN=32b, SEW=16b, LMUL=4 Byte 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 VLEN=32b, SEW=32b, LMUL=4 Byte 3 2 1 0 v4*n 0 v4*n+1 1 v4*n+2 2 v4*n+3 3 VLEN=64b, SEW=32b, LMUL=2 Byte 7 6 5 4 3 2 1 0 v2*n 1 0 v2*n+1 3 2 VLEN=64b, SEW=32b, LMUL=4 Byte 7 6 5 4 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 VLEN=128b, SEW=32b, LMUL=2 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4 VLEN=128b, SEW=32b, LMUL=4 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 3 2 1 0 v4*n+1 7 6 5 4 v4*n+2 B A 9 8 v4*n+3 F E D C
4.3. Mapping across MixedWidth Operations
The vector ISA is designed to support mixedwidth operations without
requiring explicit additional rearrangement instructions. The
recommended software strategy is to modify vtype
dynamically to keep
SEW/LMUL constant (and hence VLMAX constant) when operating on vectors
of different precision values.
The following example shows four different packed element widths (8b, 16b, 32b, 64b) in a VLEN=128b implementation. The vector register grouping factor (LMUL) is increased by the relative element size such that each group can hold the same number of vector elements (VLMAX=8 in this example) to simplify stripmining code.
Example VLEN=128b, with SEW/LMUL=16 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 vn         7 6 5 4 3 2 1 0 SEW=8b, LMUL=1/2 vn 7 6 5 4 3 2 1 0 SEW=16b, LMUL=1 v2*n 3 2 1 0 SEW=32b, LMUL=2 v2*n+1 7 6 5 4 v4*n 1 0 SEW=64b, LMUL=4 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6
The following table shows each possible constant SEW/LMUL operating point for loops with mixedwidth operations. Each column represents a constant SEW/LMUL operating point. Entries in table are the LMUL values that yield that column’s SEW/LMUL value for the datawidth on that row. In each column, an LMUL setting for a datawidth indicates that it can be aligned with the other datawidths in the same column that also have an LMUL setting, such that all have the same VLMAX.
SEW/LMUL  1  2  4  8  16  32  64  128  256  512  1024  2048  4096  8192 

SEW= 8 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 16 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 32 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 64 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 128 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 256 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW= 512 
8 
4 
2 
1 
1/2 
1/4 
1/8 

SEW=1024 
8 
4 
2 
1 
1/2 
1/4 
1/8 
Larger LMUL settings can also used to simply increase vector length to reduce instruction fetch and dispatch overheads in cases where fewer vector register groups are needed.
Note

The SEW/LMUL values of 2048 and greater are shown in the table for completeness but they do not add a useful operating point in the base architecture as they use less than the full register capacity and do not enable more architectural registers. 
4.4. Mapping with LMUL > 1 and ELEN > VLEN
If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are concatenated to form a single array of bytes, with the lowestnumbered register in the group holding the lowestaddressed bytes from the memory layout.
LMUL > 1 ELEN>VLEN, examples VLEN=32b, SEW=64b, LMUL=2 Byte 3 2 1 0 v2*n 0 v2*n+1 VLEN=32b, SEW=64b, LMUL=4 Byte 3 2 1 0 v4*n 0 v4*n+1 v4*n+2 1 v4*n+3 VLEN=32b, SEW=64b, LMUL=8 Byte 3 2 1 0 v8*n 0 v8*n+1 v8*n+2 1 v8*n+3 v8*n+4 2 v8*n+5 v8*n+6 3 v8*n+7
4.5. Mask Register Layout
A vector mask occupies only one vector register regardless of SEW and LMUL. Each element is allocated a single mask bit in a mask vector register.
Note

Earlier designs (pre0.9) had a varying number of bits per mask value (MLEN). In the 0.9 design, MLEN=1. 
4.5.1. Mask Element Locations
The mask bit for element i is located in bit i of the mask register, independent of SEW or LMUL.
VLEN=32b Byte 3 2 1 0 LMUL=1,SEW=8b 3 2 1 0 Element [03][02][01][00] Mask bit position in decimal LMUL=2,SEW=16b 1 0 [01] [00] 3 2 [03] [02] LMUL=4,SEW=32b 0 [00] 1 [01] 2 [02] 3 [03]
LMUL=2,SEW=8b 3 2 1 0 [03][02][01][00] 7 6 5 4 [07][06][05][04] LMUL=8,SEW=32b 0 [00] 1 [01] 2 [02] 3 [03] 4 [04] 5 [05] 6 [06] 7 [07] LMUL=8,SEW=8b 3 2 1 0 [03][02][01][00] 7 6 5 4 [07][06][05][04] B A 9 8 [11][10][09][08] F E D C [15][14][13][12] 13 12 11 10 [19][18][17][16] 17 16 15 14 [23][22][21][20] 1B 1A 19 18 [27][26][25][24] 1F 1E 1D 1C [31][30][29][28]
5. Vector Instruction Formats
The instructions in the vector extension fit under three existing major opcodes (LOADFP, STOREFP, AMO) and one new major opcode (OPV).
Vector loads and stores are encoding within the scalar floatingpoint load and store major opcodes (LOADFP/STOREFP). The vector load and store encodings repurpose a portion of the standard scalar floatingpoint load/store 12bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see Mask Encoding).
Format for Vector Load Instructions under LOADFP major opcode
{reg: [
{bits: 7, name: 0x7, attr: 'VL* unitstride'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'lumop'},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x7, attr: 'VLS* strided'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'rs2', attr: 'stride', type: 4},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x7, attr: 'VLX* indexed'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
Format for Vector Store Instructions under STOREFP major opcode
{reg: [
{bits: 7, name: 0x27, attr: 'VS* unitstride'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'sumop'},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x27, attr: 'VSS* strided'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'rs2', attr: 'stride', type: 4},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x27, attr: 'VSX* indexed'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
Format for Vector AMO Instructions under AMO major opcode
{reg:[
{bits: 7, name: 0x2f, attr: 'VAMO*'},
{bits: 5, name: 'vs3 / vd', attr: 'source / destination', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base', type: 4},
{bits: 5, name: 'vs2', attr: 'address', type: 2},
{bits: 1, name: 'vm'},
{bits: 1, name: 'wd'},
{bits: 5, name: 'amoop'},
]}
Formats for Vector Arithmetic Instructions under OPV major opcode
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVV'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 0x1000},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 1},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 2},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: ['OPIVI']},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 3},
{bits: 5, name: 'simm5', type: 5},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVX'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 4},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVF'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 5},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVX'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 6},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
Formats for Vector Configuration Instructions under OPV major opcode
{reg: [
{bits: 7, name: 0x57, attr: 'vsetvli'},
{bits: 5, name: 'rd', type: 4},
{bits: 3, name: 7},
{bits: 5, name: 'rs1', type: 4},
{bits: 11, name: 'zimm[10:0]', type: 5},
{bits: 1, name: '0'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'vsetvl'},
{bits: 5, name: 'rd', type: 4},
{bits: 3, name: 7},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'rs2', type: 4},
{bits: 6, name: 0x1000},
{bits: 1, name: 1},
]}
Vector instructions can have scalar or vector source operands and produce scalar or vector results, and most vector instructions can be performed either unconditionally or conditionally under a mask.
Vector loads and stores move bit patterns between vector register elements and memory. Vector arithmetic instructions operate on values held in vector register elements.
5.1. Scalar Operands
Scalar operands can be immediates, or taken from the x
registers,
the f
registers, or element 0 of a vector register. Scalar results
are written to an x
or f
register or to element 0 of a vector
register. Any vector register can be used to hold a scalar regardless
of the current LMUL setting.
Note

In a change from v0.6, the floatingpoint registers no longer
overlay the vector registers and scalars can now come from the integer
or floatingpoint registers. Not overlaying the f registers reduces
vector register pressure, avoids interactions with the standard
calling convention, simplifies highperformance scalar floatingpoint
design, and provides compatibility with the Zfinx ISA option.
Overlaying f with v would provide the advantage of lowering the
number of state bits in some implementations, but complicates
highperformance designs and would prevent compatibility with the
Zfinx ISA option.

5.2. Vector Operands
Each vector operand has an effective element width (EEW) and an effective LMUL (EMUL) that is used to determine the size and location of all the elements within a vector register group. By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL.
Some vector instructions have source and destination vector operands with the same number of elements but different widths, so that EEW and EMUL differ from SEW and LMUL respectively but EEW/EMUL = SEW/LMUL. For example, most widening arithmetic instructions have a source group with EEW=SEW and EMUL=LMUL but destination group with EEW=2*SEW and EMUL=2*LMUL. Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL but destination where EEW=SEW and EMUL=LMUL.
Vector operands or results may occupy one or more vector registers depending on EMUL, but are always specified using the lowestnumbered vector register in the group. Using other than the lowestnumbered vector register to specify a vector register group will result in an illegal instruction exception.
A destination vector register group can overlap a source vector register group only if one of the following holds:

The destination EEW equals the source EEW.

The destination EEW is smaller than the source EEW and the overlap is in the lowestnumbered part of the source register group (e.g., when LMUL=1,
vnsrl.wi v0, v0, 3
is legal, but a destination ofv1
is not). 
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highestnumbered part of the destination register group (e.g., when LMUL=8,
vzext.vf4 v0, v6
is legal, but a source ofv0
,v2
, orv4
is not).
For the purpose of register group overlap constraints, mask elements have EEW=1.
The largest vector register group used by an instruction can not be greater than 8 vector registers (i.e., EMUL≤}8), and if a vector instruction would require greater than 8 vector registers in a group, an illegal instruction exception is raised. For example, attempting a widening operation producing a widened vector register group result when LMUL=8 will raise an illegal instruction exception as this would imply a result EMUL=16.
Widened scalar values, e.g., results from widening reduction operations, are held in the first element of a vector register and have EMUL=1.
Note

Current reduction operations are defined to hold input and output values in a single vector register, with implicit EMUL of 1, so cannot accommodate using a vector register group to hold a wide scalar reduction result. This would require an independent parameter to give the EMUL for the scalar reduction element. 
5.3. Vector Masking
Masking is supported on many vector instructions. Element operations
that are masked off (inactive) never generate exceptions. The
destination vector register elements corresponding to maskedoff
elements are handled with either a maskundisturbed or maskagnostic
policy depending on the setting of the vma
bit in vtype
(Section
Vector Tail Agnostic and Vector Mask Agnostic vta
and vma
).
In the base vector extension, the mask value used to control execution
of a masked vector instruction is always supplied by vector register
v0
.
Note

Future vector extensions may provide longer instruction encodings with space for a full mask register specifier. 
The destination vector register group for a masked vector instruction
cannot overlap the source mask register (v0
), unless the destination
vector register is being written with a mask value (e.g., comparisons)
or the scalar result of a reduction. Otherwise, an illegal
instruction exception is raised.
Note

This constraint supports restart with a nonzero vstart value.

Note

Some masked instructions that target v0 which were legal in
v0.8 are illegal with the new MLEN=1 mask layout for v1.0. For
example, vadd.vv v0, v1, v2, v0.m is now always illegal; previously,
it was legal for LMUL=1.

Other vector registers can be used to hold working mask values, and mask vector logical operations are provided to perform predicate calculations.
When a mask is written with a compare result, destination mask bits
past the end of the current vector length are handled according to the
tail policy (undisturbed or agnostic) set by the vta
bit in `vtype
(Section Vector Tail Agnostic and Vector Mask Agnostic vta
and vma
).
5.3.1. Mask Encoding
Where available, masking is encoded in a singlebit vm
field in the
instruction (inst[25]
).
vm  Description 

0 
vector result, only where v0[i].LSB = 1 
1 
unmasked 
Note

In earlier proposals, vm was a twobit field vm[1:0] that
provided both true and complement masking using v0 as well as
encoding scalar operations.

Vector masking is represented in assembler code as another vector
operand, with .t
indicating if operation occurs when v0.mask[i]
is
1
. If no masking operand is specified, unmasked vector execution
(vm=1
) is assumed.
vop.v* v1, v2, v3, v0.t # enabled where v0.mask[i]=1, m=0 vop.v* v1, v2, v3 # unmasked vector operation, m=1
Note

Even though the base only supports one vector mask register v0
and only the true form of predication, the assembly syntax writes it
out in full to be compatible with future extensions that might add a
mask register specifier and supporting both true and complement
masking. The .t suffix on the masking operand also helps to visually
encode the use of a mask.

5.4. Prestart, Active, Inactive, Body, and Tail Element Definitions
The destination element indices operated on during a vector instruction’s execution can be divided into three disjoint subsets.

The prestart elements are those whose element index is less than the initial value in the
vstart
register. The prestart elements do not raise exceptions and do not update the destination vector register. 
The body elements are those whose element index is greater than or equal to the initial value in the
vstart
register, and less than the current vector length setting invl
. The body can be split into two disjoint subsets:
The active elements during a vector instruction’s execution are the elements within the body and where the current mask is enabled at that element position. The active elements can raise exceptions and update the destination vector register group.

The inactive elements are the elements within the body but where the current mask is disabled at that element position. The inactive elements do not raise exceptions and do not update any destination vector register group unless masked agnostic is specified (
vtype.vma
=1), in which case inactive elements may be overwritten with 1s.


The tail elements during a vector instruction’s execution are the elements past the current vector length setting specified in
vl
. The tail elements do not raise exceptions, and do not update any destination vector register group unless tail agnostic is specified (vtype.vta
=1), in which case tail elements may be overwritten with 1s. When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.
for element index x prestart = (0 <= x < vstart) body(x) = (vstart <= x < vl) tail(x) = (vl <= x < max(VLMAX,VLEN/SEW)) mask(x) = unmasked  v0[x].LSB == 1 active(x) = body(x) && mask(x) inactive(x) = body(x) && !mask(x)
Note

Some instructions such as vslidedown and vrgather may read
indices past vl or even VLMAX in source vector register groups. The
general policy is to return the value 0 when the index is greater than
VLMAX in the source vector register group.

6. ConfigurationSetting Instructions
One of the common approaches to handling a large number of elements is
"stripmining" where each iteration of a loop handles some number of elements,
and the iterations continue until all elements have been processed. The RISCV
vector specification provides direct, portable support for this approach.
The application specifies the total number of elements to be processed as a
candidate value for vl
, and the hardware responds via a generalpurpose
register with the (frequently smaller) number of elements that the hardware
will handle per iteration (stored in vl
), based on the microarchitectural
implementation and the vtype
setting. A straightforward loop structure,
shown in Example of stripmining and changes to SEW, depicts the ease with which the code keeps
track of the remaining number of elements and the amount per iteration handled
by hardware.
A set of instructions is provided to allow rapid configuration of the
values in vl
and vtype
to match application needs.
6.1. vsetvli
/vsetvl
instructions
The vsetvli
instruction sets the vtype
and vl
CSRs based on its
arguments, and writes the new value of vl
into rd
.
vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value
The new vtype
setting is encoded in the immediate fields of
vsetvli
and in the rs2
register for vsetvl
. The new vector
length setting is based on the requested application vector length
(AVL), which is encoded in the rs1
and rd
fields as follows:


AVL value 
Effect on 
 
!x0 
Value in 
Normal stripmining 
!x0 
x0 
~0 
Set 
x0 
x0 
Value in 
Keep existing 
When rs1
is not x0
, the AVL is an unsigned integer held in the x
register specified by rs1
, and the new vl
value is also written to
the x
register specified by rd
.
When rs1=x0
but rd!=x0
, the maximum unsigned integer value (~0
)
is used as the AVL, and the resulting VLMAX is written to vl
and
also to the x
register specified by rd
.
When rs1=x0
and rd=x0
, the current vector length in vl
is used
as the AVL, and the resulting value is written to vl
, but not to a destination register.
Note

This last form of the instruction allows the vtype register to be
changed while maintaining the current vl , provided VLMAX is not
reduced. The vl value can be reduced by this instruction if the
SEW/LMUL ratio changes causes VLMAX to shrink. This design was chosen
to ensure vl would always hold a legal value for current vtype
setting. The current vl value can be read from the vl CSR.

Formats for Vector Configuration Instructions under OPV major opcode
{reg: [
{bits: 7, name: 0x57, attr: 'vsetvli'},
{bits: 5, name: 'rd', type: 4},
{bits: 3, name: 7},
{bits: 5, name: 'rs1', type: 4},
{bits: 11, name: 'zimm[10:0]', type: 5},
{bits: 1, name: '0'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'vsetvl'},
{bits: 5, name: 'rd', type: 4},
{bits: 3, name: 7},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'rs2', type: 4},
{bits: 6, name: 0x1000},
{bits: 1, name: 1},
]}
Bits  Name  Description 

XLEN1 
vill 
Illegal value if set 
XLEN2:8 
Reserved (write 0) 

7 
vma 
Vector mask agnostic 
6 
vta 
Vector tail agnostic 
5:3 
vsew[2:0] 
Selected element width (SEW) setting 
2:0 
vlmul[2:0] 
Vector register group multiplier (LMUL) setting 
Suggested assembler names used for vsetvli immediate e8 # SEW=8b e16 # SEW=16b e32 # SEW=32b e64 # SEW=64b e128 # SEW=128b e256 # SEW=256b e512 # SEW=512b e1024 # SEW=1024b mf8 # LMUL=1/8 mf4 # LMUL=1/4 mf2 # LMUL=1/2 m1 # LMUL=1, assumed if m setting absent m2 # LMUL=2 m4 # LMUL=4 m8 # LMUL=8 Examples: vsetvli t0, a0, e8 # SEW= 8, LMUL=1 vsetvli t0, a0, e8,m2 # SEW= 8, LMUL=2 vsetvli t0, a0, e32,mf2 # SEW=32, LMUL=1/2
If the vtype
setting is not supported by the implementation, then
the vill
bit is set in vtype
, the remaining bits in vtype
are
set to zero, and the vl
register is also set to zero.
Note

Earlier drafts required a trap when setting vtype to an
illegal value. However, this would have added the first
datadependent trap on a CSR write to the ISA. The current scheme
also supports lightweight runtime interrogation of the supported
vector unit configurations by checking if vill is clear for a given
setting.

6.2. Constraints on Setting vl
The vsetvl{i}
instructions first set VLMAX according to the vtype
argument, then set vl
obeying the following constraints:

vl = AVL
ifAVL ≤ VLMAX

ceil(AVL / 2) ≤ vl ≤ VLMAX
ifAVL < (2 * VLMAX)

vl = VLMAX
ifAVL ≥ (2 * VLMAX)

Deterministic on any given implementation for same input AVL and VLMAX values

These specific properties follow from the prior rules:

vl = 0
ifAVL = 0

vl > 0
ifAVL > 0

vl ≤ VLMAX

vl ≤ AVL

a value read from
vl
when used as the AVL argument tovsetvl{i}
results in the same value invl
, provided the resultant VLMAX equals the value of VLMAX at the time thatvl
was read

Note

The For example, this permits an implementation to set 
6.3. vsetvl
Instruction
The vsetvl
variant operates similarly to vsetvli
except that it
takes a vtype
value from rs2
and can be used for context restore,
and when the vtypei
field is too small to hold the desired setting.
Note

Several active complex types can be held in different x
registers and swapped in as needed using vsetvl .

6.4. Example of stripmining and changes to SEW
The SEW and LMUL settings can be changed dynamically to provide high throughput on mixedwidth operations in a single loop.
# Example: Load 16bit values, widen multiply to 32b, shift 32b result # right by 3, store 32b values. # On entry: # a0 holds the total number of elements to process # a1 holds the address of the source array # a2 holds the address of the destination array loop: vsetvli a3, a0, e16,m4,ta,ma # vtype = 16bit integer vectors; # also update a3 with vl (# of elements this iteration) vle16.v v4, (a1) # Get 16b vector slli t1, a3, 1 # Multiply # elements this iteration by 2 bytes/source element add a1, a1, t1 # Bump pointer vwmul.vx v8, v4, x10 # Widening multiply into 32b in <v8v15> vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values vsrl.vi v8, v8, 3 vse32.v v8, (a2) # Store vector of 32b elements slli t1, a3, 2 # Multiply # elements this iteration by 4 bytes/destination element add a2, a2, t1 # Bump pointer sub a0, a0, a3 # Decrement count by vl bnez a0, loop # Any more?
7. Vector Loads and Stores
Vector loads and stores move values between vector registers and
memory. Vector loads and stores are masked and do not raise
exceptions on inactive elements. Masked vector loads do not update
inactive elements in the destination vector register group. Masked
vector stores only update active memory elements. All vector loads
and stores may generate and accept a nonzero vstart
value.
7.1. Vector Load/Store Instruction Encoding
Vector loads and stores are encoded within the scalar floatingpoint load and store major opcodes (LOADFP/STOREFP). The vector load and store encodings repurpose a portion of the standard scalar floatingpoint load/store 12bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see Mask Encoding).
Format for Vector Load Instructions under LOADFP major opcode
{reg: [
{bits: 7, name: 0x7, attr: 'VL* unitstride'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'lumop'},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x7, attr: 'VLS* strided'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'rs2', attr: 'stride', type: 4},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x7, attr: 'VLX* indexed'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
Format for Vector Store Instructions under STOREFP major opcode
{reg: [
{bits: 7, name: 0x27, attr: 'VS* unitstride'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'sumop'},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x27, attr: 'VSS* strided'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'rs2', attr: 'stride', type: 4},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x27, attr: 'VSX* indexed'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
{bits: 1, name: 'vm'},
{bits: 2, name: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
Field  Description 

rs1[4:0] 
specifies x register holding base address 
rs2[4:0] 
specifies x register holding stride 
vs2[4:0] 
specifies v register holding address offsets 
vs3[4:0] 
specifies v register holding store data 
vd[4:0] 
specifies v register destination of load 
vm 
specifies whether vector masking is enabled (0 = mask enabled, 1 = mask disabled) 
width[2:0] 
specifies size of memory elements, and distinguishes from FP scalar 
mew 
extended memory element width. See Vector Load/Store Width Encoding 
mop[1:0] 
specifies memory addressing mode 
nf[2:0] 
specifies the number of fields in each segment, for segment load/stores 
lumop[4:0]/sumop[4:0] 
are additional fields encoding variants of unitstride instructions 
Vector memory unitstride and constantstride operations directly
encode EEW of the data to be transferred statically in the instruction
to reduce the number of vtype
changes when accessing memory in a
mixedwidth routine. Indexed operations use the explicit EEW encoding
in the instruction to set the size of the indices used, and use
SEW/LMUL to specify the data width.
7.2. Vector Load/Store Addressing Modes
The base vector extension supports unitstride, strided, and
indexed (scatter/gather) addressing modes. Vector load/store base
registers and strides are taken from the GPR x
registers.
The base effective address for all vector accesses is given by the
contents of the x
register named in rs1
.
Vector unitstride operations access elements stored contiguously in memory starting from the base effective address.
Vector constantstrided operations access the first memory element at the base
effective address, and then access subsequent elements at address
increments given by the byte offset contained in the x
register
specified by rs2
.
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2
to the base effective address
to give the effective address of each element. The data vector
register group has EEW=SEW, EMUL=LMUL, while the offset vector
register group has EEW encoding in the instruction and
EMUL=(EEW/SEW)*LMUL.
The vector offset operand is treated as a vector of byteaddress offsets.
Note

The indexed operations can also be used to access fields within
a vector of objects, where the vs2 vector holds pointers to the base
of the objects and the scalar x register holds the offset of the
member field in each object. Supporting this case is why the indexed
operations were not defined to scale the element indices by the data
EEW.

If the vector offset elements are narrower than XLEN, they are zeroextended to XLEN before adding to the base effective address. If the vector offset elements are wider than XLEN, the leastsignificant XLEN bits are used in the address calculation.
Note

A profile may place a upper limit on the maximum required index EEW (e..g, only up to XLEN) smaller than ELEN, in which case an illegal instruction can be raised if the EEW is not supported. 
The vector addressing modes are encoded using the 2bit mop[1:0]
field.
mop [1:0]  Description  Opcodes  

0 
0 
unitstride 
VLE<EEW> 
0 
1 
reserved 
 
1 
0 
strided 
VLSE<EEW> 
1 
1 
indexed 
VLXEI<EEW> 
mop [1:0]  Description  Opcodes  

0 
0 
unitstride 
VSE<EEW> 
0 
1 
indexedunordered 
VSUXEI<EEW> 
1 
0 
strided 
VSSE<EEW> 
1 
1 
indexedordered 
VSXEI<EEW> 
The vector indexed store memory operations have two forms, ordered and unordered. The indexedunordered stores do not preserve element ordering on stores.
Note

The indexedunordered variant is provided as a potential implementation optimization. Implementations are free to ignore the optimization and implement indexedunordered identically to indexedordered. 
For implementations with precise vector traps, exceptions on indexedunordered stores are precise.
Additional unitstride vector addressing modes are encoded using the
5bit lumop
and sumop
fields in the unitstride load and store
instruction encodings respectively.
lumop[4:0]  Description  

0 
0 
0 
0 
0 
unitstride 
0 
0 
x 
x 
x 
reserved, x !=0 
0 
1 
0 
0 
0 
unitstride, whole registers 
0 
1 
x 
x 
x 
reserved, x !=0 
1 
0 
0 
0 
0 
unitstride faultonlyfirst 
1 
x 
x 
x 
x 
reserved, x!=0 
sumop[4:0]  Description  

0 
0 
0 
0 
0 
unitstride 
0 
0 
x 
x 
x 
reserved, x !=0 
0 
1 
0 
0 
0 
unitstride, whole registers 
0 
1 
x 
x 
x 
reserved, x !=0 
1 
x 
x 
x 
x 
reserved 
The nf[2:0]
field encodes the number of fields in each segment. For
regular vector loads and stores, nf
=0, indicating that a single
value is moved between a vector register group and memory at each
element position. Larger values in the nf
field are used to access
multiple contiguous fields within a segment as described below in
Section Vector Load/Store Segment Instructions.
Note

The nf field for segment load/stores has replaced the use of
the same bits for an address offset field. The offset can be replaced
with a single scalar integer calculation, while segment load/stores
add more powerful primitives to move items to and from memory.

The nf[2:0]
field also encodes the number of whole vector registers
to transfer for the whole vector register load/store instructions.
7.3. Vector Load/Store Width Encoding
Vector loads and stores have an EEW encoded directly in the instruction. The corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL. If the EMUL would be out of range (EMUL>8 or EMUL<1/8), an illegal instruction exception is raised. The vector register groups must have legal register specifiers for the selected EMUL, else an illegal instruction is raised.
Vector unitstride and constantstride use the EEW/EMUL encoded in the
instruction for the data values, while vector indexed loads and stores
use the EEW/EMUL encoded in the instruction for the index values and
the SEW/LMUL encoded in vtype
for the data values.
Vector loads and stores are encoded using width values that are not
claimed by the standard scalar floatingpoint loads and stores. The
mew
bit (inst[28]
) encodes expanded memory sizes of 128 bits and
above.
Vector loads and stores up to EEW=ELEN must be supported in an implementation. Using a vector load/store with an unsupported EEW raises an illegal instruction exception.
mew  width [2:0]  Mem bits  Data Reg bits  Index bits  Opcodes  

Standard scalar FP 
x 
0 
0 
1 
16 
FLEN 
 
FLH/FSH 
Standard scalar FP 
x 
0 
1 
0 
32 
FLEN 
 
FLW/FSW 
Standard scalar FP 
x 
0 
1 
1 
64 
FLEN 
 
FLD/FSD 
Standard scalar FP 
x 
1 
0 
0 
128 
FLEN 
 
FLQ/FSQ 
Vector 8b element 
0 
0 
0 
0 
8 
8 
 
VLxE8/VSxE8 
Vector 16b element 
0 
1 
0 
1 
16 
16 
 
VLxE16/VSxE16 
Vector 32b element 
0 
1 
1 
0 
32 
32 
 
VLxE32/VSxE32 
Vector 64b element 
0 
1 
1 
1 
64 
64 
 
VLxE64/VSxE64 
Vector 128b element 
1 
0 
0 
0 
128 
128 
 
VLxE128/VSxE128 
Vector 256b element 
1 
1 
0 
1 
256 
256 
 
VLxE256/VSxE256 
Vector 512b element 
1 
1 
1 
0 
512 
512 
 
VLxE512/VSxE512 
Vector 1024b element 
1 
1 
1 
1 
1024 
1024 
 
VLxE1024/VSxE1024 
Vector 8b index 
0 
0 
0 
0 
SEW 
SEW 
8 
VLxEI8/VSxEI8 
Vector 16b index 
0 
1 
0 
1 
SEW 
SEW 
16 
VLxEI16/VSxEI16 
Vector 32b index 
0 
1 
1 
0 
SEW 
SEW 
32 
VLxEI32/VSxEI32 
Vector 64b index 
0 
1 
1 
1 
SEW 
SEW 
64 
VLxEI64/VSxEI64 
Mem bits is the size of each element accessed in memory.
Data reg bits is the size of each data element accessed in register.
Note

In base V extension, only data elements widths up to max(XLEN,FLEN) must be supported. 
Index bits is the size of each index accessed in register.
Note

In base V extension, only index widths up to XLEN must be supported. 
Index bit EEW encodings larger than 64b are currently reserved.
Note

RV128 will require index EEW of 128. 
7.4. Vector UnitStride Instructions
# Vector unitstride loads and stores # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) vle8.v vd, (rs1), vm # 8bit unitstride load vle16.v vd, (rs1), vm # 16bit unitstride load vle32.v vd, (rs1), vm # 32bit unitstride load vle64.v vd, (rs1), vm # 64bit unitstride load vle128.v vd, (rs1), vm # 128bit unitstride load vle256.v vd, (rs1), vm # 256bit unitstride load vle512.v vd, (rs1), vm # 512bit unitstride load vle1024.v vd, (rs1), vm # 1024bit unitstride load # vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>) vse8.v vs3, (rs1), vm # 8bit unitstride store vse16.v vs3, (rs1), vm # 16bit unitstride store vse32.v vs3, (rs1), vm # 32bit unitstride store vse64.v vs3, (rs1), vm # 64bit unitstride store vse128.v vs3, (rs1), vm # 128bit unitstride store vse256.v vs3, (rs1), vm # 256bit unitstride store vse512.v vs3, (rs1), vm # 512bit unitstride store vse1024.v vs3, (rs1), vm # 1024bit unitstride store
7.5. Vector Strided Instructions
# Vector strided loads and stores # vd destination, rs1 base address, rs2 byte stride vlse8.v vd, (rs1), rs2, vm # 8bit strided load vlse16.v vd, (rs1), rs2, vm # 16bit strided load vlse32.v vd, (rs1), rs2, vm # 32bit strided load vlse64.v vd, (rs1), rs2, vm # 64bit strided load vlse128.v vd, (rs1), rs2, vm # 128bit strided load vlse256.v vd, (rs1), rs2, vm # 256bit strided load vlse512.v vd, (rs1), rs2, vm # 512bit strided load vlse1024.v vd, (rs1), rs2, vm # 1024bit strided load # vs3 store data, rs1 base address, rs2 byte stride vsse8.v vs3, (rs1), rs2, vm # 8bit strided store vsse16.v vs3, (rs1), rs2, vm # 16bit strided store vsse32.v vs3, (rs1), rs2, vm # 32bit strided store vsse64.v vs3, (rs1), rs2, vm # 64bit strided store vsse128.v vs3, (rs1), rs2, vm # 128bit strided store vsse256.v vs3, (rs1), rs2, vm # 256bit strided store vsse512.v vs3, (rs1), rs2, vm # 512bit strided store vsse1024.v vs3, (rs1), rs2, vm # 1024bit strided store
Negative and zero strides are supported.
Where element stores overlap due to either zero stride, or strides smaller than the element size when misaligned elements are supported, element stores are performed in element order.
7.6. Vector Indexed Instructions
# Vector indexed loads and stores # vd destination, rs1 base address, vs2 indices vlxei8.v vd, (rs1), vs2, vm # 8bit indexed load of SEW data vlxei16.v vd, (rs1), vs2, vm # 16bit indexed load of SEW data vlxei32.v vd, (rs1), vs2, vm # 32bit indexed load of SEW data vlxei64.v vd, (rs1), vs2, vm # 64bit indexed load of SEW data # Vector ordered indexed store instructions # vs3 store data, rs1 base address, vs2 indices vsxei8.v vs3, (rs1), vs2, vm # ordered 8bit indexed store of SEW data vsxei16.v vs3, (rs1), vs2, vm # ordered 16bit indexed store of SEW data vsxei32.v vs3, (rs1), vs2, vm # ordered 32bit indexed store of SEW data vsxei64.v vs3, (rs1), vs2, vm # ordered 64bit indexed store of SEW data # Vector unorderedindexed store instructions vsuxei8.v vs3, (rs1), vs2, vm # unordered 8bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm # unordered 16bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm # unordered 32bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm # unordered 64bit indexed store of SEW data
Note

The assembler syntax for indexed loads and stores uses
ei x instead of e x to indicate the statically encoded EEW
is of the index not the data.

7.7. Unitstride FaultOnlyFirst Loads
The unitstride faultonlyfirst load instructions are used to
vectorize loops with datadependent exit conditions ("while" loops).
These instructions execute as a regular load except that they will
only take a trap caused by a synchronous exception on element 0. If
an element > 0 raises an exception, that element and all following
elements in the destination vector register are not modified, and the
vector length vl
is reduced to the index of the element that would
have raised an exception.
# Vector unitstride faultonlyfirst loads and stores # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) vle8ff.v vd, (rs1), vm # 8bit unitstride faultonlyfirst load vle16ff.v vd, (rs1), vm # 16bit unitstride faultonlyfirst load vle32ff.v vd, (rs1), vm # 32bit unitstride faultonlyfirst load vle64ff.v vd, (rs1), vm # 64bit unitstride faultonlyfirst load vle128ff.v vd, (rs1), vm # 128bit unitstride faultonlyfirst load vle256ff.v vd, (rs1), vm # 256bit unitstride faultonlyfirst load vle512ff.v vd, (rs1), vm # 512bit unitstride faultonlyfirst load vle1024ff.v vd, (rs1), vm # 1024bit unitstride faultonlyfirst load
strlen example using unitstride faultonlyfirst instruction # size_t strlen(const char *str) # a0 holds *str strlen: mv a3, a0 # Save start loop: vsetvli a1, x0, e8,m8, ta,ma # Vector of bytes of maximum length vle8ff.v v8, (a3) # Load bytes csrr a1, vl # Get bytes read vmseq.vi v0, v8, 0 # Set v0[i] where v8[i] = 0 vfirst.m a2, v0 # Find first set bit add a3, a3, a1 # Bump pointer bltz a2, loop # Not found? add a0, a0, a1 # Sum start + bump add a3, a3, a2 # Add index sub a0, a3, a0 # Subtract start address+bump ret
Note

Strided and scatter/gather faultonlyfirst instructions are not provided due to lack of encoding space, and they can also represent a larger security hole, allowing software to check multiple random pages for accessibility without experiencing a trap. The unitstride versions only allow probing a region immediately contiguous to a known region, and so do not appreciably impact security. It is possible that security mitigations can be implemented to allow faultonlyfirst variants of noncontiguous accesses in future vector extensions. 
Even when an exception is not raised, implementations are permitted to process
fewer than vl
elements and reduce vl
accordingly, but if vstart
=0 and
vl
>0, then at least one element must be processed.
Note

vl is not modified if element 0 raises an exception.

Implementations should not reduce vl
and instead set a nonzero
vstart
value when the faultonlyfirst instruction takes a trap due
to an interrupt.
7.8. Vector Load/Store Segment Instructions
This instruction subset is given the ISA string name Zvlsseg
.
Note

This set of instructions is included in the base "V" extension used for the Unix profile. 
The vector load/store segment instructions move multiple contiguous fields in memory to and from consecutively numbered vector registers.
Note

These operations support operations on "arrayofstructures" datatypes by unpacking each field in a structure into separate vector registers. 
The threebit nf
field in the vector instruction encoding is an
unsigned integer that contains one less than the number of fields per
segment, NFIELDS.
nf[2:0]  NFIELDS  

0 
0 
0 
1 
0 
0 
1 
2 
0 
1 
0 
3 
0 
1 
1 
4 
1 
0 
0 
5 
1 
0 
1 
6 
1 
1 
0 
7 
1 
1 
1 
8 
The EMUL setting must be such that EMUL * NFIELDS ≤ 8, otherwise an illegal instruction exception is raised.
Note

The product EMUL * NFIELDS represents the number of underlying vector registers that will be touched by a segmented load or store instruction. This constraint makes this total no larger than 1/4 of the architectural register file, and the same as for regular operations with EMUL=8. This constraint could be weakened in a future draft. 
Each field will be held in successively numbered vector register groups. When EMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field’s vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number).
Note

An earlier version imposed a vector register number constraint, but this decreased ability to make use of all registers when NFIELDS was not a power of 2. 
If the vector register numbers accessed by the segment load or store would increment past 31, then an illegal instruction exception is raised.
Note

This constraint is to help provide forwardcompatibility with a future longer instruction encoding that has more addressable vector registers. 
The vl
register gives the number of structures to move, which is
equal to the number of elements transferred to each vector register
group. Masking is also applied at the level of whole structures.
If a trap is taken, vstart
is in units of structures.
7.8.1. Vector UnitStride Segment Loads and Stores
The vector unitstride load and store segment instructions move packed contiguous segments ("arrayofstructures") into multiple destination vector register groups.
Note

For segments with heterogeneoussized fields, software can later unpack fields using additional instructions after the segment load brings the values into the separate vector registers. 
The assembler prefixes vlseg
/vsseg
are used for unitstride
segment loads and stores respectively.
# Format vlseg<nf>e<eew>.v vd, (rs1), vm # Unitstride segment load template vsseg<nf>e<eew>.v vs3, (rs1), vm # Unitstride segment store template # Examples vlseg8e8.v vd, (rs1), vm # Load eight vector registers with eight byte fields. vsseg3e32.v vs3, (rs1), vm # Store packed vector of 3*4byte segments from vs3,vs3+1,vs3+2 to memory
For loads, the vd
register will hold the first field loaded from the
segment. For stores, the vs3
register is read to provide the first
field to be stored in each segment.
# Example 1 # Memory structure holds packed RGB pixels (24bit data structure, 8bpp) vsetvli a1, t0, e8, ta,ma vlseg3e8.v v8, (a0), vm # v8 holds the red pixels # v9 holds the green pixels # v10 holds the blue pixels # Example 2 # Memory structure holds complex values, 32b for real and 32b for imaginary vsetvli a1, t0, e32, ta,ma vlseg2e32.v v8, (a0), vm # v8 holds real # v9 holds imaginary
There are also faultonlyfirst versions of the unitstride instructions.
# Template for vector faultonlyfirst unitstride segment loads and stores. vlseg<nf>e<eew>ff.v vd, (rs1), vm # Unitstride faultonlyfirst segment loads
7.8.2. Vector Strided Segment Loads and Stores
Vector strided segment loads and stores move contiguous segments where
each segment is separated by the bytestride offset given in the rs2
GPR argument.
Note

Negative and zero strides are supported. 
# Format vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores # Examples vsetvli a1, t0, e8, ta,ma vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i], # and bytes at addresses x5+i*x6+1 into v5[i], # and bytes at addresses x5+i*x6+2 into v6[i]. # Examples vsetvli a1, t0, e32, ta,ma vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6 # and words from v3[i] to address x5+i*x6+4
For strided segment stores where the byte stride is such that segments could overlap in memory, the segments must appear to be written in element order.
7.8.3. Vector Indexed Segment Loads and Stores
Vector indexed segment loads and stores move contiguous segments where
each segment is located at an address given by adding the scalar base
address in the rs1
field to byte offsets in vector register vs2
.
The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL.
# Format vlxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed segment loads vsxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed segment stores # Examples vsetvli a1, t0, e8, ta,ma vlxseg3ei32.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i], # and bytes at addresses x5+v3[i]+1 into v5[i], # and bytes at addresses x5+v3[i]+2 into v6[i]. # Examples vsetvli a1, t0, e32, ta,ma vsxseg2ei32.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i] # and words from v3[i] to address x5+v5[i]+4
For vector indexed segment loads, the destination vector register
groups cannot overlap the source vector register group (specified by
vs2
), else an illegal instruction exception is raised.
Note

This constraint supports restart of indexed segment loads that raise exceptions partway through loading a structure. 
Only ordered indexed segment stores are provided. The segments must appear to be written in element order.
7.9. Vector Load/Store Whole Register Instructions
Format for Vector Load Whole Register Instructions under LOADFP major opcode
{reg: [
{bits: 7, name: 0x07, attr: 'VL*R*'},
{bits: 5, name: 'vd', attr: 'destination of load', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 8, attr: 'lumop'},
{bits: 1, name: 1, attr: 'vm'},
{bits: 2, name: 0x10000, attr: 'mop'},
{bits: 1, name: 'mew'},
{bits: 3, name: 'nf'},
]}
{reg: [
{bits: 7, name: 0x27, attr: 'VS*R*'},
{bits: 5, name: 'vs3', attr: 'store data', type: 2},
{bits: 3, name: 0x1000},
{bits: 5, name: 'rs1', attr: 'base address', type: 4},
{bits: 5, name: 8, attr: 'sumop'},
{bits: 1, name: 1, attr: 'vm'},
{bits: 2, name: 0x100, attr: 'mop'},
{bits: 1, name: 0x100, attr: 'mew'},
{bits: 3, name: 'nf'},
]}
These instructions load and store whole vector registers (i.e., VLEN bits), optionally as vector register groups.
Note

These instructions are intended to be used to save and restore
vector registers when the type or length of the current contents of
the vector register is not known, or where modifying vl and vtype
would be costly. Examples include compiler register spills, vector
function calls where values are passed in vector registers, interrupt
handlers, and OS context switches. Software can determine the number
of bytes transferred by reading the vlenb register.

The load instructions have an EEW encoded in the mew
and width
fields following the pattern of regular unitstride loads. However,
the instructions are defined to always move vectors of bytes as if
SEW=8, regardless of EEW encoding. Pseudoinstructions are provide
for whole register load instructions that correspond to EEW=8. The
vector whole register store instructions are encoded similar to
unmasked unitstride store of elements with EEW=8.
Note

For the purposes of opaque save and restore of register state, the instructions have been defined as only moving byte vectors (SEW=8) between registers and memory. For littleendian machines, EEW does not change how bytes are moved between architectural vector register locations and memory locations, and so these instructions can reuse the regular unitstride load implementation for EEW. For littleendian machines, the encoded EEW can be used as a HINT to indicate the destination register group will next be accessed with this EEW, which aids implementations that rearrange data internally. Bigendian machines are affected by EEW, so must always treat wholeregister loads as SEW=8 load as stores always use SEW=8. Bigendian machines that rearrange internal data internally will not be able to exploit the hint. 
When transferring a single register, the instructions operate with an
evl
=VLEN/EEW, regardless of current
settings in vtype
and vl
. No elements are transferred if vstart
≥ VLEN/EEW. The usual property that no elements are written if
vstart
≥ vl
does not apply to these instructions.
The instructions operate similarly to unmasked unitstride load and
store instructions of elements, with the base address passed in the
scalar x
register specified by rs1
.
The nf
field encodes how many vector registers to load and store.
The encoded number of registers must be a power of 2 and the vector
register numbers must be aligned as with a vector register group,
otherwise an illegal instruction exception is raised. The nf
field
encodes the number of vector registers to transfer (1, 2, 4, 8),
numbered successively after the base. When multiple registers are
transferred, the lowestnumbered vector register is held in the
lowestnumbered memory addresses and successive vector register
numbers are placed contiguously in memory.
Implementations are allowed to raise a misaligned address exception if the base address is not naturally aligned to the encoded EEW.
Note

Allowing misaligned exceptions to be raised simplifies the implementation of these instructions. Software that uses whole register moves will generally use a much larger alignment than the minimum required, so this does not complicate software use cases. 
# Format of whole register move instructions. vl1r.v v3, (a0) # Pseudo instruction equal to vl1re8.v vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 vl1re128.v v3, (a0) vl1re256.v v3, (a0) vl1re512.v v3, (a0) vl1re1024.v v3, (a0) vl2r.v v2, (a0) # Pseudo instruction equal to vl2re8.v v2, (a0) vl2re8.v v2, (a0) # Load v2v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) # Load v2v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) # Load v2v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) # Load v2v3 with 2*VLEN/64 doublewords held at address in a0 vl2re128.v v2, (a0) vl2re256.v v2, (a0) vl2re512.v v2, (a0) vl2re1024.v v2, (a0) vl4r.v v4, (a0) # Pseudo instruction equal to vl4re8.v vl4re8.v v4, (a0) # Load v4v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0) vl4re128.v v4, (a0) vl4re256.v v4, (a0) vl4re512.v v4, (a0) vl4re1024.v v4, (a0) vl8r.v v8, (a0) # Pseudo instruction equal to vl8re8.v vl8re8.v v8, (a0) # Load v8v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0) vl8re128.v v8, (a0) vl8re256.v v8, (a0) vl8re512.v v8, (a0) vl8re1024.v v8, (a0) vs1r.v v3, (a1) # Store v3 to address in a1 vs2r.v v2, (a1) # Store v2v3 to address in a1 vs4r.v v4, (a1) # Store v4v7 to address in a1 vs8r.v v8, (a1) # Store v8v15 to address in a1
Implementations should raise illegal instruction exceptions on vl<nf>r
instructions for EEW values that are not supported.
Note

The task group has thus far agreed to include only the single
register load/store variant with nf =0 in the base V extension, but
is still discussing whether to mandate the multiple register version.

Note

These instructions can be implemented as unitstride
loads/stores of vector register groups, where EEW is 8, nf encodes
EMUL, and vl = VLMAX for EEW and EMUL.

8. Vector AMO Operations
This instruction subset is given the ISA string Zvamo
.
Note

This set of instructions is included in the base "V" extension used for the Unix profile. 
If vector AMO instructions are supported, then the scalar Zaamo instructions (atomic operations from the standard A extension) must be present.
Vector AMO operations are encoded using the unused width encodings under the standard AMO major opcode. Each active element performs an atomic readmodifywrite of a single memory location.
Format for Vector AMO Instructions under AMO major opcode
{reg:[
{bits: 7, name: 0x2f, attr: 'VAMO*'},
{bits: 5, name: 'vs3 / vd', attr: 'source / destination', type: 2},
{bits: 3, name: 'width'},
{bits: 5, name: 'rs1', attr: 'base', type: 4},
{bits: 5, name: 'vs2', attr: 'address', type: 2},
{bits: 1, name: 'vm'},
{bits: 1, name: 'wd'},
{bits: 5, name: 'amoop'},
]}
vs2[4:0] specifies v register holding address vs3/vd[4:0] specifies v register holding source operand and destination vm specifies vector mask width[2:0] specifies size of index elements, and distinguishes from scalar AMO amoop[4:0] specifies the AMO operation wd specifies whether the original memory value is written to vd (1=yes, 0=no)
The vs2
vector register supplies the byte offset of each element,
while the vs3
vector register supplies the source data for the
atomic memory operation.
AMOs have the same index EEW scheme as indexed operations, except
without the mew
bit, which is is assumed to be zero, so offsets can
have EEW=8,16,32,64 only. A vector of byte offsets in register vs2
is added to the scalar base register in rs1
to give the addresses
of the AMO operations.
The data register vs3
used dynamic SEW and MUL setting.
If the wd
bit is set, the vd
register is written with the initial
value of the memory element. If the wd
bit is clear, the vd
register is not written.
Note

When wd is clear, the memory system does not need to return
the original memory value, and the original values in vd will be
preserved.

Note

The AMOs were defined to overwrite source data partly to reduce total memory pipeline read port count for implementations with register renaming. Also to support the same addressing mode as vector indexed operations, and because vector AMOs are less likely to need results given that the primary use is parallel inmemory reductions. 
Vector AMOs operate as if aq
and rl
bits were zero on each element
with regard to ordering relative to other instructions in the same
hart.
Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction.
Width [2:0]  Index EEW  Mem data bits  Reg data bits  Opcode  

Standard scalar AMO 
0 
1 
0 
 
32 
XLEN 
AMO*.W 
Standard scalar AMO 
0 
1 
1 
 
64 
XLEN 
AMO*.D 
Standard scalar AMO 
1 
0 
0 
 
128 
XLEN 
AMO*.Q 
Vector AMO 
0 
0 
0 
8 
SEW 
SEW 
VAMO*EI8.V 
Vector AMO 
1 
0 
1 
16 
SEW 
SEW 
VAMO*EI16.V 
Vector AMO 
1 
1 
0 
32 
SEW 
SEW 
VAMO*EI32.V 
Vector AMO 
1 
1 
1 
64 
SEW 
SEW 
VAMO*EI64.V 
Index bits is the EEW of the offsets.
Mem bits is the size of element accessed in memory
Reg bits is the size of element accessed in register
If index EEW is less than XLEN, then addresses in the vector vs2
are
zeroextended to XLEN. If index EEW is greater than XLEN, an illegal
instruction exception is raised.
Vector AMO instructions are only supported for the memory data element widths (in SEW) supported by AMOs in the implementation’s scalar architecture. Other element widths raise an illegal instruction exception.
The vector amoop[4:0]
field uses the same encoding as the scalar
5bit AMO instruction field, except that LR and SC are not supported.
amoop  opcode  

0 
0 
0 
0 
1 
vamoswap 
0 
0 
0 
0 
0 
vamoadd 
0 
0 
1 
0 
0 
vamoxor 
0 
1 
1 
0 
0 
vamoand 
0 
1 
0 
0 
0 
vamoor 
1 
0 
0 
0 
0 
vamomin 
1 
0 
1 
0 
0 
vamomax 
1 
1 
0 
0 
0 
vamominu 
1 
1 
1 
0 
0 
vamomaxu 
The assembly syntax uses x0
in the destination register position to
indicate the return value is not required (wd=0
).
# Vector AMOs for index EEW=8 vamoswapei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoswapei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoaddei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoaddei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoxorei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoxorei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoandei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoandei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoorei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoorei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominuei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominuei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxuei8.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxuei8.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 # Vector AMOs for index EEW=16 vamoswapei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoswapei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoaddei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoaddei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoxorei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoxorei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoandei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoandei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoorei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoorei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominuei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominuei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxuei16.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxuei16.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 # Vector AMOs for index EEW=32 vamoswapei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoswapei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoaddei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoaddei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoxorei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoxorei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoandei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoandei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoorei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoorei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominuei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominuei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxuei32.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxuei32.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 # Vector AMOs for index EEW=64 vamoswapei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoswapei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoaddei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoaddei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoxorei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoxorei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoandei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoandei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamoorei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamoorei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamominuei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamominuei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxuei64.v vd, (rs1), vs2, vd, v0.t # Write original value to register, wd=1 vamomaxuei64.v x0, (rs1), vs2, vs3, v0.t # Do not write original value to register, wd=0
9. Vector Memory Alignment Constraints
If the elements accessed by a vector memory instruction are not naturally aligned to the memory element size, either an address misaligned exception is raised on that element or the element is transferred successfully.
Vector memory accesses follow the same rules for atomicity as scalar memory accesses.
10. Vector Memory Consistency Model
Vector memory instructions appear to execute in program order on the local hart. Vector memory instructions follow RVWMO at the instruction level, and element operations are ordered within the instruction as if performed by an elementordered sequence of syntactically independent scalar instructions. Vector indexedordered stores write elements to memory in element order. Vector indexedunordered stores do not preserve element order for writes within a single vector store instruction.
Note

Need to flesh out details. 
11. Vector Arithmetic Instruction Formats
The vector arithmetic instructions use a new major opcode (OPV =
1010111_{2}) which neighbors OPFP. The threebit funct3
field is
used to define subcategories of vector instructions.
Formats for Vector Arithmetic Instructions under OPV major opcode
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVV'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 0x1000},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 1},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 2},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: ['OPIVI']},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 3},
{bits: 5, name: 'simm5', type: 5},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVX'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 4},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVF'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 5},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVX'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 6},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
11.1. Vector Arithmetic Instruction encoding
The funct3
field encodes the operand type and source locations.
funct3[2:0]  Operands  Source of scalar(s)  

0 
0 
0 
OPIVV 
vectorvector 
 
0 
0 
1 
OPFVV 
vectorvector 
 
0 
1 
0 
OPMVV 
vectorvector 
 
0 
1 
1 
OPIVI 
vectorimmediate 
imm[4:0] 
1 
0 
0 
OPIVX 
vectorscalar 
GPR x register rs1 
1 
0 
1 
OPFVF 
vectorscalar 
FP f register rs1 
1 
1 
0 
OPMVX 
vectorscalar 
GPR x register rs1 
1 
1 
1 
OPCFG 
scalarsimms 
GPR x register rs1 & rs2/imm 
Integer operations are performed using unsigned or two’scomplement signed integer arithmetic depending on the opcode.
Note

In this discussion, fixedpoint operations are considered to be integer operations. 
All standard vector floatingpoint arithmetic operations follow the
IEEE754/2008 standard. All vector floatingpoint operations use the
dynamic rounding mode in the frm
register. If the frm
field
contains an invalid rounding mode, attempting to execute any vector
floatingpoint instruction, even those that do not depend on the
rounding mode, or when vl
=0, or when vstart
≥ vl
, will raise
an illegal instruction exception.
Note

All vector floatingpoint code will rely on a valid value in
frm . Making all vector FP instructions report exceptions when the
rounding mode is invalid simplifies control logic.

Vectorvector operations take two vectors of operands from vector
register groups specified by vs2
and vs1
respectively.
Vectorscalar operations can have three possible forms, but in all
cases take one vector of operands from a vector register group
specified by vs2
and a second scalar source operand from one of
three alternative sources.

For integer operations, the scalar can be a 5bit immediate encoded in the
rs1
field. The value is signextended to SEW bits, unless otherwise specified. 
For integer operations, the scalar can be taken from the scalar
x
register specified byrs1
. If XLEN>SEW, the leastsignificant SEW bits of thex
register are used, unless otherwise specified. If XLEN<SEW, the value from thex
register is signextended to SEW bits. 
For floatingpoint operations, the scalar can be taken from a scalar
f
register. If FLEN > SEW, the value in thef
registers is checked for a valid NaNboxed value, in which case the leastsignificant SEW bits of thef
register are used, else the canonical NaN value is used. If execution is attempted of a vector instruction where any floatingpoint vector operand’s EEW is not a supported floatingpoint type width (which includes when FLEN < SEW), an illegal instruction exception is raised.
Note

Some instructions zeroextend the 5bit immediate, and denote this
by naming the immediate uimm in the assembly syntax.

Note

The proposed Zfinx variants will take the floatingpoint scalar
argument from the x registers.

Vector arithmetic instructions are masked under control of the vm
field.
# Assembly syntax pattern for vector binary arithmetic instructions # Operations returning vector results, masked by vm (v0.t, <nothing>) vop.vv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vop.vx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1] vop.vi vd, vs2, imm, vm # integer vectorimmediate vd[i] = vs2[i] op imm vfop.vv vd, vs2, vs1, vm # FP vectorvector operation vd[i] = vs2[i] fop vs1[i] vfop.vf vd, vs2, rs1, vm # FP vectorscalar operation vd[i] = vs2[i] fop f[rs1]
Note

In the encoding, vs2 is the first operand, while rs1/simm5
is the second operand. This is the opposite to the standard scalar
ordering. This arrangement retains the existing encoding conventions
that instructions that read only one scalar register, read it from
rs1 , and that 5bit immediates are sourced from the rs1 field.

# Assembly syntax pattern for vector ternary arithmetic instructions (multiplyadd) # Integer operations overwriting sum input vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vs2[i] + vd[i] # Integer operations overwriting product input vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vd[i] + vs2[i] # Floatingpoint operations overwriting sum input vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vs2[i] + vd[i] # Floatingpoint operations overwriting product input vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vd[i] + vs2[i]
Note

For ternary multiplyadd operations, the assembler syntax always
places the destination vector register first, followed by either rs1
or vs1 , then vs2 . This ordering provides a more natural reading
of the assembler for these ternary operations, as the multiply
operands are always next to each other.

11.2. Widening Vector Arithmetic Instructions
A few vector arithmetic instructions are defined to be widening operations where the destination elements have EEW=2*SEW and EMUL=2*LMUL.
The first operand can be either single or doublewidth. These are
generally written with a vw*
prefix on the opcode or vfw*
for
vector floatingpoint operations.
Assembly syntax pattern for vector widening arithmetic instructions # Doublewidth result, two singlewidth sources: 2*SEW = SEW op SEW vwop.vv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vwop.vx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1] # Doublewidth result, first source doublewidth, second source singlewidth: 2*SEW = 2*SEW op SEW vwop.wv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vwop.wx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1]
Note

Originally, a w suffix was used on opcode, but this could be
confused with the use of a w suffix to mean wordsized operations in
doubleword integers, so the w was moved to prefix.

Note

The floatingpoint widening operations were changed to vfw*
from vwf* to be more consistent with any scalar widening
floatingpoint operations that will be written as fw* .

Note

For integer multiplyadd, another possible widening option
increases the size of the accumulator to EEW=4*SEW (i.e., 4*SEW +=
SEW*SEW). These would be distinguished by a vw4* prefix on the
opcode. These are not included at this time, but are a possible
addition to spec.

The destination vector register group results are arranged as if both SEW and LMUL were at twice their current settings (i.e., EEW=2*SEW, EMUL=2*LMUL).
For all widening instructions, the destination EEW and EMUL values must be a supported configuration, otherwise an illegal instruction exception is raised.
The destination vector register group must be specified using a vector register number that is valid for the destination’s EMUL, otherwise an illegal instruction exception is raised.
Note

This constraint is necessary to support restart with nonzero
vstart .

Note

For the vw<op>.wv vd, vs2, vs1 format instructions, it is legal
for vd to equal vs2.

11.3. Narrowing Vector Arithmetic Instructions
A few instructions are provided to convert doublewidth source vectors into singlewidth destination vectors. These instructions convert a vector register group with EEW/EMUL=2*SEW/2*LMUL to a vector register group with the current LMUL/SEW vectors/elements.
If EEW > ELEN or EMUL > 8, an illegal instruction exception is raised.
Note

An alternative design decision would have been to treat LMUL as defining the size of the source vector register group. The choice here is motivated by the belief the chosen approach will require fewer LMUL changes. 
The source and destination vector register groups have to be specified with a vector register number that is legal for the source and destination EMUL values respectively, otherwise an illegal instruction exception is raised.
Where there is a second source vector register group (specified by
vs1
), this has the same (narrower) width as the result (i.e.,
EEW=SEW).
Note

It is safe to overwrite a second source vector register group with the same LMUL and element width as the result. 
A vn*
prefix on the opcode is used to distinguish these instructions
in the assembler, or a vfn*
prefix for narrowing floatingpoint
opcodes. The doublewidth source vector register group is signified
by a w
in the source operand suffix (e.g., vnsra.wv
)
Note

Comparison operations that set a mask register are also implicitly a narrowing operation. 
12. Vector Integer Arithmetic Instructions
A set of vector integer arithmetic instructions is provided.
12.1. Vector SingleWidth Integer Add and Subtract
Vector integer add and subtract are provided. Reversesubtract instructions are also provided for the vectorscalar forms.
# Integer adds. vadd.vv vd, vs2, vs1, vm # Vectorvector vadd.vx vd, vs2, rs1, vm # vectorscalar vadd.vi vd, vs2, imm, vm # vectorimmediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vectorvector vsub.vx vd, vs2, rs1, vm # vectorscalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1  vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm  vs2[i]
12.2. Vector Widening Integer Add/Subtract
The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign or zeroextended before forming the doublewidth sum.
# Widening unsigned integer add/subtract, 2*SEW = SEW +/ SEW vwaddu.vv vd, vs2, vs1, vm # vectorvector vwaddu.vx vd, vs2, rs1, vm # vectorscalar vwsubu.vv vd, vs2, vs1, vm # vectorvector vwsubu.vx vd, vs2, rs1, vm # vectorscalar # Widening signed integer add/subtract, 2*SEW = SEW +/ SEW vwadd.vv vd, vs2, vs1, vm # vectorvector vwadd.vx vd, vs2, rs1, vm # vectorscalar vwsub.vv vd, vs2, vs1, vm # vectorvector vwsub.vx vd, vs2, rs1, vm # vectorscalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/ SEW vwaddu.wv vd, vs2, vs1, vm # vectorvector vwaddu.wx vd, vs2, rs1, vm # vectorscalar vwsubu.wv vd, vs2, vs1, vm # vectorvector vwsubu.wx vd, vs2, rs1, vm # vectorscalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/ SEW vwadd.wv vd, vs2, vs1, vm # vectorvector vwadd.wx vd, vs2, rs1, vm # vectorscalar vwsub.wv vd, vs2, vs1, vm # vectorvector vwsub.wx vd, vs2, rs1, vm # vectorscalar
Note

An integer value can be doubled in width using the widening add
instructions with a scalar operand of x0 . Can define assembly
pseudoinstructions vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm and
vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm .

12.3. Vector Integer Extension
The vector integer extension instructions zero or signextend a source vector integer operand with EEW less than SEW to fill SEWsized elements in the destination. The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL. The destination has EEW equal to SEW and EMUL equal to LMUL.
vzext.vf2 vd, vs2, vm # Zeroextend SEW/2 source to SEW destination vsext.vf2 vd, vs2, vm # Signextend SEW/2 source to SEW destination vzext.vf4 vd, vs2, vm # Zeroextend SEW/4 source to SEW destination vsext.vf4 vd, vs2, vm # Signextend SEW/4 source to SEW destination vzext.vf8 vd, vs2, vm # Zeroextend SEW/8 source to SEW destination vsext.vf8 vd, vs2, vm # Signextend SEW/8 source to SEW destination
If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, an illegal instruction exception is raised.
12.4. Vector Integer AddwithCarry / SubtractwithBorrow Instructions
To support multiword integer arithmetic, instructions that operate on a carry bit are provided. For each operation (add or subtract), two instructions are provided: one to provide the result (SEW width), and the second to generate the carry output (single bit encoded as a mask boolean).
The carry inputs and outputs are represented using the mask register
layout as described in Section Mask Register Layout. Due to
encoding constraints, the carry input must come from the implicit v0
register, but carry outputs can be written to any vector register that
respects the source/destination overlap restrictions.
vadc
and vsbc
add or subtract the source operands and the carryin or
borrowin, and write the result to vector register vd
.
These instructions are encoded as masked instructions (vm=0
), but they operate
on and write back all body elements.
Encodings corresponding to the unmasked versions (vm=1
) are reserved.
vmadc
and vmsbc
add or subtract the source operands, optionally add the
carryin or subtract the borrowin if masked (vm=0
), and write the result back
to mask register vd
.
If unmasked (vm=1
), there is no carryin or borrowin.
These instructions operate on and write back all body elements, even if
masked.
# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0[i].LSB vadc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = vs2[i] + x[rs1] + v0[i].LSB vadc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = vs2[i] + imm + v0[i].LSB vadc.vim vd, vs2, imm, v0 # Vectorimmediate # Produce carry out in mask register format # vd[i] = carry_out(vs2[i] + vs1[i] + v0[i].LSB) vmadc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = carry_out(vs2[i] + x[rs1] + v0[i].LSB) vmadc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = carry_out(vs2[i] + imm + v0[i].LSB) vmadc.vim vd, vs2, imm, v0 # Vectorimmediate # vd[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vectorvector, no carryin # vd[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vectorscalar, no carryin # vd[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vectorimmediate, no carryin
Because implementing a carry propagation requires executing two instructions with unchanged inputs, destructive accumulations will require an additional move to obtain correct results.
# Example multiword arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 # Calc new sum vmcpy.m v0, v1 # Move temp carry into v0 for next word
The subtract with borrow instruction vsbc
performs the equivalent
function to support long word arithmetic for subtraction. There are
no subtract with immediate instructions.
# Produce difference with borrow. # vd[i] = vs2[i]  vs1[i]  v0[i].LSB vsbc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = vs2[i]  x[rs1]  v0[i].LSB vsbc.vxm vd, vs2, rs1, v0 # Vectorscalar # Produce borrow out in mask register format # vd[i] = borrow_out(vs2[i]  vs1[i]  v0[i].LSB) vmsbc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = borrow_out(vs2[i]  x[rs1]  v0[i].LSB) vmsbc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = borrow_out(vs2[i]  vs1[i]) vmsbc.vv vd, vs2, vs1 # Vectorvector, no borrowin # vd[i] = borrow_out(vs2[i]  x[rs1]) vmsbc.vx vd, vs2, rs1 # Vectorscalar, no borrowin
For vmsbc
, the borrow is defined to be 1 iff the difference, prior to
truncation, is negative.
For vadc
and vsbc
, an illegal instruction exception is raised
if the destination vector register is v0
.
Note

This constraint corresponds to the constraint on masked vector operations that overwrite the mask register. 
12.5. Vector Bitwise Logical Instructions
# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vectorvector vand.vx vd, vs2, rs1, vm # vectorscalar vand.vi vd, vs2, imm, vm # vectorimmediate vor.vv vd, vs2, vs1, vm # Vectorvector vor.vx vd, vs2, rs1, vm # vectorscalar vor.vi vd, vs2, imm, vm # vectorimmediate vxor.vv vd, vs2, vs1, vm # Vectorvector vxor.vx vd, vs2, rs1, vm # vectorscalar vxor.vi vd, vs2, imm, vm # vectorimmediate
Note

With an immediate of 1, scalarimmediate forms of the vxor
instruction provide a bitwise NOT operation. This can be provided as
an assembler pseudoinstruction vnot.v .

12.6. Vector SingleWidth Bit Shift Instructions
A full complement of vector shift instructions are provided, including logical shift left, and logical (zeroextending) and arithmetic (signextending) shift right.
# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vectorvector vsll.vx vd, vs2, rs1, vm # vectorscalar vsll.vi vd, vs2, uimm, vm # vectorimmediate vsrl.vv vd, vs2, vs1, vm # Vectorvector vsrl.vx vd, vs2, rs1, vm # vectorscalar vsrl.vi vd, vs2, uimm, vm # vectorimmediate vsra.vv vd, vs2, vs1, vm # Vectorvector vsra.vx vd, vs2, rs1, vm # vectorscalar vsra.vi vd, vs2, uimm, vm # vectorimmediate
The low lg2(SEW) bits of the vector or scalar shift amount value are used; immediates are zeroextended.
12.7. Vector Narrowing Integer Right Shift Instructions
The narrowing right shifts extract a smaller field from a wider
operand and have both zeroextending (srl
) and signextending
(sra
) forms. The shift amount can come from a vector or a scalar
x
register or a 5bit immediate. The low lg2(2*SEW) bits of the
vector or scalar shift amount value are used (e.g., the low 6 bits for
a SEW=64bit to SEW=32bit narrowing operation). The immediate forms
zeroextend their immediate operand.
# Narrowing shift right logical, SEW = (2*SEW) >> SEW vnsrl.wv vd, vs2, vs1, vm # vectorvector vnsrl.wx vd, vs2, rs1, vm # vectorscalar vnsrl.wi vd, vs2, uimm, vm # vectorimmediate # Narrowing shift right arithmetic, SEW = (2*SEW) >> SEW vnsra.wv vd, vs2, vs1, vm # vectorvector vnsra.wx vd, vs2, rs1, vm # vectorscalar vnsra.wi vd, vs2, uimm, vm # vectorimmediate
Note

It could be useful to add support for n4 variants, where the
destination is 1/4 width of source.

Note

An integer value can be halved in width using the narrowing integer
shift instructions with a scalar operand of x0. Can define assembly
pseudoinstructions vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm .

12.8. Vector Integer Comparison Instructions
The following integer compare instructions write 1 to the destination
mask register element if the comparison evaluates to true, and 0
otherwise. The destination mask vector is always held in a single
vector register, with a layout of elements as described in Section
Mask Register Layout. The destination mask vector register
may be the same as the source vector mask register (v0
).
# Set if equal vmseq.vv vd, vs2, vs1, vm # Vectorvector vmseq.vx vd, vs2, rs1, vm # vectorscalar vmseq.vi vd, vs2, imm, vm # vectorimmediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vectorvector vmsne.vx vd, vs2, rs1, vm # vectorscalar vmsne.vi vd, vs2, imm, vm # vectorimmediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vectorvector vmsltu.vx vd, vs2, rs1, vm # Vectorscalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vectorvector vmslt.vx vd, vs2, rs1, vm # vectorscalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vectorvector vmsleu.vx vd, vs2, rs1, vm # vectorscalar vmsleu.vi vd, vs2, imm, vm # Vectorimmediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vectorvector vmsle.vx vd, vs2, rs1, vm # vectorscalar vmsle.vi vd, vs2, imm, vm # vectorimmediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vectorscalar vmsgtu.vi vd, vs2, imm, vm # Vectorimmediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vectorscalar vmsgt.vi vd, vs2, imm, vm # Vectorimmediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vectorscalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vectorscalar
The following table indicates how all comparisons are implemented in native machine code.
Comparison Assembler Mapping Assembler Pseudoinstruction va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below va < i vmsle{u}.vi vd, va, i1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i1, vm vmsge{u}.vi vd, va, i, vm va, vb vector register groups x scalar integer register i immediate
Note

The immediate forms of vmslt{u}.vi are not provided as the
immediate value can be decreased by 1 and the vmsle{u}.vi variants
used instead. The vmsle.vi range is 16 to 15, resulting in an
effective vmslt.vi range of 15 to 16. The vmsleu.vi range is 0
to 15 giving an effective vmsltu.vi range of 1 to 16 (Note,
vmsltu.vi with immediate 0 is not useful as it is always
false). Because the 5bit vector immediates are always signextended,
vmsleu.vi also supports unsigned immediate values in the range
2^{SEW}16 to 2^{SEW}1 , allowing corresponding vmsltu.vi
comparisons against unsigned immediates in the range 2^{SEW}15 to
2^{SEW} . Note that vlsltu.vi with immediate 2^{SEW} is not useful
as it is always true.

Similarly, vmsge{u}.vi
is not provided and the comparison is
implemented using vmsgt{u}.vi
with the immediate decremented by one.
The resulting effective vmsge.vi
range is 15 to 16, and the
resulting effective vmsgeu.vi
range is 1 to 16 (Note, vmsgeu.vi
with
immediate 0 is not useful as it is always true).
Note

The vmsgt forms for register scalar and immediates are provided
to allow a single comparison instruction to provide the correct
polarity of mask value without using additional mask logical
instructions.

To reduce encoding space, the vmsge{u}.vx
form is not directly
provided, and so the va ≥ x
case requires special treatment.
Note

The vmsge{u}.vx could potentially be encoded in a
nonorthogonal way under the unused OPIVI variant of vmslt{u} . These
would be the only instructions in OPIVI that use a scalar `x`register
however. Alternatively, a further two funct6 encodings could be used,
but these would have a different operand format (writes to mask
register) than others in the same group of 8 funct6 encodings. The
current PoR is to omit these instructions and to synthesize where
needed as described below.

The vmsge{u}.vx
operation can be synthesized by reducing the
value of x
by 1 and using the vmsgt{u}.vx
instruction, when it is
known that this will not underflow the representation in x
.
Sequences to synthesize `vmsge{u}.vx` instruction va >= x, x > minimum addi t0, x, 1; vmsgt{u}.vx vd, va, t0, vm
The above sequence will usually be the most efficient implementation,
but assembler pseudoinstructions can be provided for cases where the
range of x
is unknown.
unmasked va >= x pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd masked va >= x, vd != v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 masked va >= x, vd == v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt masked va >= x, any vd pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vt, v0, vt; vmandnot.mm vd, vd, v0; vmor.mm vd, vt, vd The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction
Comparisons effectively AND in the mask, e.g,
# (a < b) && (b < c) in two instructions vmslt.vv v0, va, vb # All body elements written vmslt.vv v0, vb, vc, v0.t # Only update at set mask
12.9. Vector Integer Min/Max Instructions
Signed and unsigned integer minimum and maximum instructions are supported.
# Unsigned minimum vminu.vv vd, vs2, vs1, vm # Vectorvector vminu.vx vd, vs2, rs1, vm # vectorscalar # Signed minimum vmin.vv vd, vs2, vs1, vm # Vectorvector vmin.vx vd, vs2, rs1, vm # vectorscalar # Unsigned maximum vmaxu.vv vd, vs2, vs1, vm # Vectorvector vmaxu.vx vd, vs2, rs1, vm # vectorscalar # Signed maximum vmax.vv vd, vs2, vs1, vm # Vectorvector vmax.vx vd, vs2, rs1, vm # vectorscalar
12.10. Vector SingleWidth Integer Multiply Instructions
The singlewidth multiply instructions perform a SEWbit*SEWbit
multiply and return an SEWbitwide result. The mulh
versions
write the high word of the product to the destination register.
# Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm # Vectorvector vmul.vx vd, vs2, rs1, vm # vectorscalar # Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm # Vectorvector vmulh.vx vd, vs2, rs1, vm # vectorscalar # Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm # Vectorvector vmulhu.vx vd, vs2, rs1, vm # vectorscalar # Signed(vs2)Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm # Vectorvector vmulhsu.vx vd, vs2, rs1, vm # vectorscalar
Note

There is no vmulhus opcode to return high half of
unsignedvector * signedscalar product.

Note

The current vmulh* opcodes perform simple fractional
multiplies, but with no option to scale, round, and/or saturate the
result. Can consider changing definition of vmulh , vmulhu ,
vmulhsu to use vxrm rounding mode when discarding low half of
product. There is no possibility of overflow in this case.

12.11. Vector Integer Divide Instructions
The divide and remainder instructions are equivalent to the RISCV standard scalar integer multiply/divides, with the same results for extreme inputs.
# Unsigned divide. vdivu.vv vd, vs2, vs1, vm # Vectorvector vdivu.vx vd, vs2, rs1, vm # vectorscalar # Signed divide vdiv.vv vd, vs2, vs1, vm # Vectorvector vdiv.vx vd, vs2, rs1, vm # vectorscalar # Unsigned remainder vremu.vv vd, vs2, vs1, vm # Vectorvector vremu.vx vd, vs2, rs1, vm # vectorscalar # Signed remainder vrem.vv vd, vs2, vs1, vm # Vectorvector vrem.vx vd, vs2, rs1, vm # vectorscalar
Note

The decision to include integer divide and remainder was contentious. The argument in favor is that without a standard instruction, software would have to pick some algorithm to perform the operation, which would likely perform poorly on some microarchitectures versus others. 
Note

There is no instruction to perform a "scalar divide by vector" operation. 
12.12. Vector Widening Integer Multiply Instructions
The widening integer multiply instructions return the full 2*SEWbit product from an SEWbit*SEWbit multiply.
# Widening signedinteger multiply vwmul.vv vd, vs2, vs1, vm# vectorvector vwmul.vx vd, vs2, rs1, vm # vectorscalar # Widening unsignedinteger multiply vwmulu.vv vd, vs2, vs1, vm # vectorvector vwmulu.vx vd, vs2, rs1, vm # vectorscalar # Widening signedunsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm # vectorvector vwmulsu.vx vd, vs2, rs1, vm # vectorscalar
12.13. Vector SingleWidth Integer MultiplyAdd Instructions
The integer multiplyadd instructions are destructive and are provided
in two forms, one that overwrites the addend or minuend
(vmacc
, vnmsac
) and one that overwrites the first multiplicand
(vmadd
, vnmsub
).
The low half of the product is added or subtracted from the third operand.
Note

"sac" is intended to be read as "subtract from accumulator". The
opcode is "vnmsac" to match the (unfortunately counterintuitive)
floatingpoint fnmsub instruction definition. Similarly for the
"vnmsub" opcode.

# Integer multiplyadd, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Integer multiplysub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vs2[i]) + vd[i] # Integer multiplyadd, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] # Integer multiplysub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i]
12.14. Vector Widening Integer MultiplyAdd Instructions
The widening integer multiplyadd instructions add a SEWbit*SEWbit multiply result to (from) a 2*SEWbit value and produce a 2*SEWbit result. All combinations of signed and unsigned multiply operands are supported.
# Widening unsignedinteger multiplyadd, overwrite addend vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signedinteger multiplyadd, overwrite addend vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signedunsignedinteger multiplyadd, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Widening unsignedsignedinteger multiplyadd, overwrite addend vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
12.15. Vector Integer Merge Instructions
The vector integer merge instructions combine two source operands
based on a mask. Unlike regular arithmetic instructions, the
merge operates on all body elements (i.e., the set of elements from
vstart
up to the current vector length in vl
).
The vmerge
instructions are always masked (vm=0
).
The instructions combine two
sources as follows. At elements where the mask value is zero, the
first operand is copied to the destination element, otherwise the
second operand is copied to the destination element. The first
operand is always a vector register group specified by vs2
. The
second operand is a vector register group specified by vs1
or a
scalar x
register specified by rs1
or a 5bit signextended
immediate.
vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]
12.16. Vector Integer Move Instructions
The vector integer move instructions copy a source operand to a vector
register group.
The vmv.v.v
variant copies a vector register group, whereas the vmv.v.x
and vmv.v.i
variants splat a scalar register or immediate to all active
elements of the destination vector register group.
These instructions are always unmasked (vm=1
).
The first operand specifier (vs2
) must contain v0
, and any other vector
register number in vs2
is reserved.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = rs1 vmv.v.i vd, imm # vd[i] = imm
Note

Mask values can be widened into SEWwidth elements using a
sequence vmv.v.i vd, 0; vmerge.vim vd, vd, 1, v0 .

Note

The vector integer move instructions share the encoding with the vector
merge instructions, but with vm=1 and vs2=v0 .

Note

The form vmv.v.v vd, vd , which leaves body elements unchanged,
is used as a hint to indicate that the register will be used
with an EEW equal to SEW. Implementations that internally reorganize
data according to EEW can shuffle the internal representation
according to SEW. Implementations that do not internally reorganize
data can dynamically elide this instruction, and treat as a NOP.

13. Vector FixedPoint Arithmetic Instructions
The preceding set of integer arithmetic instructions is extended to support fixedpoint arithmetic.
A fixedpoint number is a two’scomplement signed or unsigned integer interpreted as the numerator in a fraction with an implicit denominator. The fixedpoint instructions are intended to be applied to the numerators; it is the responsibility of software to manage the denominators. An Nbit element can hold two’scomplement signed integers in the range 2^{N1}…+2^{N1}1, and unsigned integers in the range 0 … +2^{N}1. The fixedpoint instructions help preserve precision in narrow operands by supporting scaling and rounding, and can handle overflow by saturating results into the destination format range.
Note

The widening integer operations described above can also be used to remove the possibility of overflow. 
13.1. Vector SingleWidth Saturating Add and Subtract
Saturating forms of integer add and subtract are provided, for both
signed and unsigned integers. If the result would overflow the
destination, the result is replaced with the closest representable
value, and the vxsat
bit is set.
# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vectorvector vsaddu.vx vd, vs2, rs1, vm # vectorscalar vsaddu.vi vd, vs2, imm, vm # vectorimmediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vectorvector vsadd.vx vd, vs2, rs1, vm # vectorscalar vsadd.vi vd, vs2, imm, vm # vectorimmediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vectorvector vssubu.vx vd, vs2, rs1, vm # vectorscalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vectorvector vssub.vx vd, vs2, rs1, vm # vectorscalar
13.2. Vector SingleWidth Averaging Add and Subtract
The averaging add and subtract instructions right shift the result by
one bit and round off the result according to the setting in vxrm
.
Both unsigned and signed versions are provided.
For vaaddu
, vaadd
, and vasub
, there can be no overflow in the result.
For vasubu
, overflow is ignored.
# Averaging add # Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) # Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) # Averaging subtract # Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i]  vs1[i], 1) vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i]  x[rs1], 1) # Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i]  vs1[i], 1) vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i]  x[rs1], 1)
13.3. Vector SingleWidth Fractional Multiply with Rounding and Saturation
The signed fractional multiply instruction produces a 2*SEW product of
the two SEW inputs, then shifts the result right by SEW1 bits,
rounding these bits according to vxrm
, then saturates the result to
fit into SEW bits. If the result causes saturation, the vxsat
bit
is set.
# Signed saturating and rounding fractional multiply # See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW1)) vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW1))
Note

When multiplying two Nbit signed numbers, the largest magnitude is obtained for 2^{N1} * 2^{N1} producing a result +2^{2N2}, which has a single (zero) sign bit when held in 2N bits. All other products have two sign bits in 2N bits. To retain greater precision in N result bits, the product is shifted right by one bit less than N, saturating the largest magnitude result but increasing result precision by one bit for all other products. 
13.4. Vector SingleWidth Scaling Shift Instructions
These instructions shift the input value right, and round off the
shifted out bits according to vxrm
. The scaling right shifts have
both zeroextending (vssrl
) and signextending (vssra
) forms.
The low lg2(SEW) bits of the vector or scalar shift amount value are used;
immediates are zeroextended.
# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)
13.5. Vector Narrowing FixedPoint Clip Instructions
The vnclip
instructions are used to pack a fixedpoint value into a
narrower destination. The instructions support rounding, scaling, and
saturation into the final destination format.
The second argument (vector element, scalar value, immediate value) gives the amount to right shift the source as in the narrowing shift instructions, which provides the scaling. The low lg2(2*SEW) bits of the vector or scalar shift amount value are used (e.g., the low 6 bits for a SEW=64bit to SEW=32bit narrowing operation). The immediate forms zeroextend their immediate operand.
# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5))
For vnclipu
/vnclip
, the rounding mode is specified in the vxrm
CSR. Rounding occurs around the leastsignificant bit of the
destination and before saturation.
For vnclipu
, the shifted rounded source value is treated as an
unsigned integer and saturates if the result would overflow the
destination viewed as an unsigned integer.
For vnclip
, the shifted rounded source value is treated as a signed
integer and saturates if the result would overflow the destination viewed
as a signed integer.
If any destination element is saturated, the vxsat
bit is set in the
vxsat
register.
14. Vector FloatingPoint Instructions
The standard vector floatingpoint instructions treat 16bit, 32bit, 64bit, and 128bit elements as IEEE754/2008compatible values. If the EEW of a vector floatingpoint operand does not correspond to a supported IEEE floatingpoint type, an illegal instruction exception is raised.
Note

The floatingpoint element widths that are supported depend on the profile. 
Vector floatingpoint instructions require the presence of base scalar floatingpoint extensions corresponding to the supported vector floatingpoint element widths.
Note

Profiles supporting 16bit halfprecision floatingpoint values
will also have to implement scalar halfprecision floatingpoint
support in the f registers.

If the floatingpoint unit status field mstatus.FS
is Off
then any
attempt to execute a vector floatingpoint instruction will raise an
illegal instruction exception. Any vector floatingpoint instruction
that modifies any floatingpoint extension state (i.e., floatingpoint
CSRs or f
registers) must set mstatus.FS
to Dirty
.
The vector floatingpoint instructions have the same behavior as the scalar floatingpoint instructions with regard to NaNs.
Scalar values for vectorscalar operations can be sourced from the
standard scalar f
registers, as described in Section
Vector Arithmetic Instruction encoding.
14.1. Vector FloatingPoint Exception Flags
A vector floatingpoint exception at any active floatingpoint element
sets the standard FP exception flags in the fflags
register. Inactive
elements do not set FP exception flags.
14.2. Vector SingleWidth FloatingPoint Add/Subtract Instructions
# Floatingpoint add vfadd.vv vd, vs2, vs1, vm # Vectorvector vfadd.vf vd, vs2, rs1, vm # vectorscalar # Floatingpoint subtract vfsub.vv vd, vs2, vs1, vm # Vectorvector vfsub.vf vd, vs2, rs1, vm # Vectorscalar vd[i] = vs2[i]  f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalarvector vd[i] = f[rs1]  vs2[i]
14.3. Vector Widening FloatingPoint Add/Subtract Instructions
# Widening FP add/subtract, 2*SEW = SEW +/ SEW vfwadd.vv vd, vs2, vs1, vm # vectorvector vfwadd.vf vd, vs2, rs1, vm # vectorscalar vfwsub.vv vd, vs2, vs1, vm # vectorvector vfwsub.vf vd, vs2, rs1, vm # vectorscalar # Widening FP add/subtract, 2*SEW = 2*SEW +/ SEW vfwadd.wv vd, vs2, vs1, vm # vectorvector vfwadd.wf vd, vs2, rs1, vm # vectorscalar vfwsub.wv vd, vs2, vs1, vm # vectorvector vfwsub.wf vd, vs2, rs1, vm # vectorscalar
14.4. Vector SingleWidth FloatingPoint Multiply/Divide Instructions
# Floatingpoint multiply vfmul.vv vd, vs2, vs1, vm # Vectorvector vfmul.vf vd, vs2, rs1, vm # vectorscalar # Floatingpoint divide vfdiv.vv vd, vs2, vs1, vm # Vectorvector vfdiv.vf vd, vs2, rs1, vm # vectorscalar # Reverse floatingpoint divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalarvector, vd[i] = f[rs1]/vs2[i]
14.5. Vector Widening FloatingPoint Multiply
# Widening floatingpoint multiply vfwmul.vv vd, vs2, vs1, vm # vectorvector vfwmul.vf vd, vs2, rs1, vm # vectorscalar
14.6. Vector SingleWidth FloatingPoint Fused MultiplyAdd Instructions
All four varieties of fused multiplyadd are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand.
# FP multiplyaccumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP negate(multiplyaccumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i])  vd[i] vfnmacc.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i])  vd[i] # FP multiplysubtractaccumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i])  vd[i] vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i])  vd[i] # FP negate(multiplysubtractaccumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i]) + vd[i] # FP multiplyadd, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] # FP negate(multiplyadd), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i])  vs2[i] vfnmadd.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vd[i])  vs2[i] # FP multiplysub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i])  vs2[i] vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i])  vs2[i] # FP negate(multiplysub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vd[i]) + vs2[i]
Note

It would be possible to use the two unused rounding modes in the scalar FP FMA encoding to provide a few nondestructive FMAs. However, this would be the only maskable operation with three inputs and separate output. 
14.7. Vector Widening FloatingPoint Fused MultiplyAdd Instructions
The widening floatingpoint fused multiplyadd instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide.
# FP widening multiplyaccumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP widening negate(multiplyaccumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i])  vd[i] vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i])  vd[i] # FP widening multiplysubtractaccumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i])  vd[i] vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i])  vd[i] # FP widening negate(multiplysubtractaccumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i]) + vd[i]
14.8. Vector FloatingPoint SquareRoot Instruction
This is a unary vectorvector instruction.
# Floatingpoint square root vfsqrt.v vd, vs2, vm # Vectorvector square root
14.9. Vector FloatingPoint Reciprocal SquareRoot Estimate Instruction
# Floatingpoint reciprocal squareroot estimate to 7 bits. vfrsqrte7.v vd, vs2, vm
This is a unary vectorvector instruction that returns an estimate of 1/sqrt(x) accurate to 7 bits.
The following table describes the instruction’s behavior for all classes of floatingpoint inputs:
Input  Output  Exceptions raised 

∞ ≤ x < 0.0 
canonical NaN 
NV 
0.0 
∞ 
DZ 
+0.0 
+∞ 
DZ 
+0.0 < x < +∞ 
estimate of 1/sqrt(x) 

+∞ 
+0.0 

qNaN 
canonical NaN 

sNaN 
canonical NaN 
NV 
Note

All positive normal and subnormal inputs produce normal outputs. 
Note

The output value is independent of the dynamic rounding mode. 
For the nonexceptional cases, the low bit of the exponent and the six high bits of significand (after the leading one) are concatenated and used to address the following table. The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero. Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup. The output exponent is chosen to make the result approximate the reciprocal of the square root of the argument.
More precisely, the result is computed as follows. Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise. If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit. The output exponent equals floor((3*B  1  the normalized input exponent) / 2). The output sign equals the input sign.
The following table gives the seven MSBs of the output significand as a function of the LSB of the normalized input exponent and the six MSBs of the normalized input significand; the other bits of the output significand are zero.
exp[0] 
sig[MSB : 6] 
sig_out[MSB : 7] 
0 
0 
52 
1 
51 

2 
50 

3 
48 

4 
47 

5 
46 

6 
44 

7 
43 

8 
42 

9 
41 

10 
40 

11 
39 

12 
38 

13 
36 

14 
35 

15 
34 

16 
33 

17 
32 

18 
31 

19 
30 

20 
30 

21 
29 

22 
28 

23 
27 

24 
26 

25 
25 

26 
24 

27 
23 

28 
23 

29 
22 

30 
21 

31 
20 

32 
19 

33 
19 

34 
18 

35 
17 

36 
16 

37 
16 

38 
15 

39 
14 

40 
14 

41 
13 

42 
12 

43 
12 

44 
11 

45 
10 

46 
10 

47 
9 

48 
9 

49 
8 

50 
7 

51 
7 

52 
6 

53 
6 

54 
5 

55 
4 

56 
4 

57 
3 

58 
3 

59 
2 

60 
2 

61 
1 

62 
1 

63 
0 

1 
0 
127 
1 
125 

2 
123 

3 
121 

4 
119 

5 
118 

6 
116 

7 
114 

8 
113 

9 
111 

10 
109 

11 
108 

12 
106 

13 
105 

14 
103 

15 
102 

16 
100 

17 
99 

18 
97 

19 
96 

20 
95 

21 
93 

22 
92 

23 
91 

24 
90 

25 
88 

26 
87 

27 
86 

28 
85 

29 
84 

30 
83 

31 
82 

32 
80 

33 
79 

34 
78 

35 
77 

36 
76 

37 
75 

38 
74 

39 
73 

40 
72 

41 
71 

42 
70 

43 
70 

44 
69 

45 
68 

46 
67 

47 
66 

48 
65 

49 
64 

50 
63 

51 
63 

52 
62 

53 
61 

54 
60 

55 
59 

56 
59 

57 
58 

58 
57 

59 
56 

60 
56 

61 
55 

62 
54 

63 
53 
Note

For example, when SEW=32, vfrsqrte7(0x00718abc (≈ 1.043e38)) = 0x5f080000 (≈ 9.800e18), and vfrsqrte7(0x7f765432 (≈ 3.274e38)) = 0x1f820000 (≈ 5.506e20). 
Note

The 7 bit accuracy was chosen as it requires 0,1,2,3 NewtonRaphson iterations to converge to close to bfloat16, FP16, FP32, FP64 accuracy respectively. Future instructions can be defined with greater estimate accuracy. 
14.10. Vector FloatingPoint Reciprocal Estimate Instruction
# Floatingpoint reciprocal estimate to 7 bits. vfrece7.v vd, vs2, vm
This is a unary vectorvector instruction that returns an estimate of 1/x accurate to 7 bits.
The following table describes the instruction’s behavior for all classes of floatingpoint inputs, where B is the exponent bias:
Input (x)  Rounding Mode  Output (y ≈ 1/x)  Exceptions raised 

∞ 
any 
0.0 

2^{B+1} < x ≤ 2^{B} (normal) 
any 
2^{(B+1)} ≥ y > 2^{B} (subnormal, sig=01…) 

2^{B} < x ≤ 2^{B1} (normal) 
any 
2^{B} ≥ y > 2^{B+1} (subnormal, sig=1…) 

2^{B1} < x ≤ 2^{B+1} (normal) 
any 
2^{B+1} ≥ y > 2^{B1} (normal) 

2^{B+1} < x ≤ 2^{B} (subnormal, sig=1…) 
any 
2^{B1} ≥ y > 2^{B} (normal) 

2^{B} < x ≤ 2^{(B+1)} (subnormal, sig=01…) 
any 
2^{B} ≥ y > 2^{B+1} (normal) 

2^{(B+1)} < x < 0.0 (subnormal, sig=00…) 
RUP, RTZ 
greatestmag. negative finite value 
NX, OF 
2^{(B+1)} < x < 0.0 (subnormal, sig=00…) 
RDN, RNE, RMM 
∞ 
NX, OF 
0.0 
any 
∞ 
DZ 
+0.0 
any 
+∞ 
DZ 
+0.0 < x < 2^{(B+1)} (subnormal, sig=00…) 
RUP, RNE, RMM 
+∞ 
NX, OF 
+0.0 < x < 2^{(B+1)} (subnormal, sig=00…) 
RDN, RTZ 
greatest finite value 
NX, OF 
2^{(B+1)} ≤ x < 2^{B} (subnormal, sig=01…) 
any 
2^{B+1} > y ≥ 2^{B} (normal) 

2^{B} ≤ x < 2^{B+1} (subnormal, sig=1…) 
any 
2^{B} > y ≥ 2^{B1} (normal) 

2^{B+1} ≤ x < 2^{B1} (normal) 
any 
2^{B1} > y ≥ 2^{B+1} (normal) 

2^{B1} ≤ x < 2^{B} (normal) 
any 
2^{B+1} > y ≥ 2^{B} (subnormal, sig=1…) 

2^{B} ≤ x < 2^{B+1} (normal) 
any 
2^{B} > y ≥ 2^{(B+1)} (subnormal, sig=01…) 

+∞ 
any 
+0.0 

qNaN 
any 
canonical NaN 

sNaN 
any 
canonical NaN 
NV 
Note

Subnormal inputs with magnitude at least 2^{(B+1)} produce normal outputs; other subnormal inputs produce infinite outputs. Normal inputs with magnitude at least 2^{B1} produce subnormal outputs; other normal inputs produce normal outputs. 
Note

The output value depends on the dynamic rounding mode when the overflow exception is raised. 
For the nonexceptional cases, the seven high bits of significand (after the leading one) are used to address the following table. The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero. Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup. The output exponent is chosen to make the result approximate the reciprocal of the argument, and subnormal outputs are denormalized accordingly.
More precisely, the result is computed as follows. Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise. The normalized output exponent equals (2*B  1  the normalized input exponent). If the normalized output exponent is outside the range [1, 2*B], the result corresponds to one of the exceptional cases in the table above.
If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit. Otherwise, the normalized input significand equals the input significand. The following table gives the seven MSBs of the normalized output significand as a function of the seven MSBs of the normalized input significand; the other bits of the normalized output significand are zero.
sig[MSB : 7] 
sig_out[MSB : 7] 
0 
127 
1 
125 
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