Contributors include: Alon Amid, Krste Asanovic, Allen Baum, Alex Bradbury, Tony Brewer, Chris Celio, Aliaksei Chapyzhenka, Silviu Chiricescu, Ken Dockser, Bob Dreyer, Roger Espasa, Sean Halle, John Hauser, David Horner, Bruce Hoult, Bill Huffman, Constantine Korikov, Ben Korpan, Robin Kruppe, Yunsup Lee, Guy Lemieux, Filip Moc, Rich Newell, Albert Ou, David Patterson, Colin Schmidt, Alex Solomatnikov, Steve Wallach, Andrew Waterman, Jim Wilson.
Known issues with current version:

encoding needs better formatting

vector memory consistency model needs to be clarified

interaction with privileged architectures
1. Introduction
This document describes the draft of the RISCV base vector extension. The document describes all the individual features of the base vector extension.
Note

This is a draft of a stable proposal for the vector specification to be used for implementation and evaluation. Once the draft label is removed, version 0.8 is intended to be stable enough to begin developing toolchains, functional simulators, and initial implementations, though will continue to evolve with minor changes and updates. 
The term base vector extension is used informally to describe the standard set of vector ISA components. This draft spec is intended to capture how a certain vector function will be implemented as vector instructions, but to not yet determine what set of vector instructions are mandatory for a given platform.
Note

Each actual platform profile will formally specify the mandatory components of any vector extension adopted by that platform. The base vector extension given the single letter name "V" will be that intended for use in standard server/applicationprocessor platform profiles. Other platforms, including embedded platforms, may choose to implement subsets of these extensions. The exact set of mandatory supported instructions for an implementation to be compliant with a given profile is subject to change until each profile spec is ratified. 
The base vector extension is designed to act as a base for additional vector extensions in various domains, including cryptography and machine learning.
2. Implementationdefined Constant Parameters
Each hart supporting the vector extension defines three parameters:

The maximum size of a single vector element in bits, ELEN, which must be a power of 2.

The number of bits in a vector register, VLEN ≥ ELEN, which must be a power of 2.

The striping distance in bits, SLEN, which must be VLEN ≥ SLEN ≥ 32, and which must be a power of 2.
Note

Platform profiles may set further constraints on these parameters, for example, requiring that ELEN ≥ max(XLEN,FLEN), or requiring a minimum VLEN value, or setting an SLEN value. 
Note

There is a proposal to drop the constraint that VLEN must be a power of two. 
Note

There is a proposal to allow ELEN to vary with LMUL. 
The ISA supports writing binary code that under certain constraints will execute portably on harts with different values for these parameters.
Note

Code can be written that will expose differences in implementation parameters. 
Note

Thread contexts with active vector state cannot be migrated during execution between harts that have any difference in VLEN, ELEN, or SLEN parameters. 
3. Vector Extension Programmer’s Model
The vector extension adds 32 vector registers, and six unprivileged
CSRs (vstart
, vxsat
, vxrm
, vtype
, vl
, vlenb
) to a base scalar
RISCV ISA. If the base scalar ISA does not include floatingpoint,
then a fcsr
register is also added to hold mirrors of the vxsat
and vxrm
CSRs as explained below.
Address  Privilege  Name  Description 

0x008 
URW 
vstart 
Vector start position 
0x009 
URW 
vxsat 
FixedPoint Saturate Flag 
0x00A 
URW 
vxrm 
FixedPoint Rounding Mode 
0xC20 
URO 
vl 
Vector length 
0xC21 
URO 
vtype 
Vector data type register 
0xC22 
URO 
vlenb 
VLEN/8 (vector register length in bytes) 
3.1. Vector Registers
The vector extension adds 32 architectural vector registers,
v0
v31
to the base scalar RISCV ISA.
Each vector register has a fixed VLEN bits of state.
Note

Zfinx ("F in X") is a new ISA option under consideration where floatingpoint instructions take their arguments from the integer register file. The 0.8 vector extension is also compatible with this option. 
3.2. Vector Context Status in mstatus
A vector context status field, VS
, is added to mstatus[24:23]
and shadowed
in sstatus[24:23]
. It is defined analogously to the floatingpoint context
status field, FS
.
Attempts to execute any vector instruction, or to access the vl
,
vtype
, vlenb
, or vstart
CSRs, raise an illegalinstruction
exception when the VS
field is set to Off.
When the VS
field is set to Initial or Clean, executing any
instruction that changes vector state, including the vl
, vtype
,
and vstart
registers, will change VS
to Dirty.
Note

Implementations may also change VS field to Dirty at any time,
even when there is no change in vector state. Accurate setting of the
VS field is an optimization.

Attempts to access an f
register or the fcsr
, vxsat
, or vxrm
CSRs raise an
illegalinstruction exception when the floatingpoint context status FS
is
set to Off.
Note

Vector instructions that read or write an f register or fcsr , vxsat , or vxrm raise
an illegalinstruction exception if either VS or FS is set to Off.
However, these CSRs can be read or written using CSRaccess instructions when
FS is set to a value other than Off, irrespective of the value of VS .

If FS
is set to Initial or Clean, executing any instruction that changes
fcsr
, vxsat
, vxrm
, or an f
register will change FS
to Dirty.
Note

Contextswitching code must save all of fcsr if FS is set to Dirty.

Note

Fixedpointonly implementations, which would not benefit from lazy
floatingpoint save/restore, might hardwire the FS field to Dirty to
reduce cost. In this case, fcsr would always be accessible.

3.3. Vector type register, vtype
The readonly XLENwide vector type CSR, vtype
provides the
default type used to interpret the contents of the vector register
file, and can only be updated by vsetvl{i}
instructions. The vector
type also determines the organization of elements in each vector
register, and how multiple vector registers are grouped.
Note

Earlier drafts allowed the vtype register to be written using
regular CSR writes. Allowing updates only via the vsetvl{i}
instructions simplifies maintenance of the vtype register state.

In the base vector extension, the vtype
register has three fields,
vill
, vsew[2:0]
, and vlmul[1:0]
.
Bits  Name  Description 

XLEN1 
vill 
Illegal value if set 
XLEN2:7 
Reserved (write 0) 

6:5 
vediv[1:0] 
Used by EDIV extension 
4:2 
vsew[2:0] 
Standard element width (SEW) setting 
1:0 
vlmul[1:0] 
Vector register group multiplier (LMUL) setting 
Note

The smallest base implementation requires storage for only four
bits of storage in vtype , two bits for vsew[1:0] and two bits for
vlmul[1:0] . The illegal value represented by vill can be encoded
using the illegal 64bit combination in vsew[1:0] without requiring
an additional storage bit.

Note

The vediv[1:0] field is used by the EDIV extension described below. 
Note

Further standard and custom extensions to the vector base will extend these fields to support a greater variety of data types. 
Note

It is anticipated that an extended 64bit instruction encoding would allow these fields to be specified statically in the instruction encoding. 
3.3.1. Vector standard element width vsew
The value in vsew
sets the dynamic standard element width
(SEW). By default, a vector register is viewed as being divided into
VLEN / SEW standardwidth elements. In the base vector extension,
only SEW up to max(XLEN,FLEN) are required to be supported.
vsew[2:0]  SEW  

0 
0 
0 
8 
0 
0 
1 
16 
0 
1 
0 
32 
0 
1 
1 
64 
1 
0 
0 
128 
1 
0 
1 
256 
1 
1 
0 
512 
1 
1 
1 
1024 
SEW  Elements per vector register 

64 
2 
32 
4 
16 
8 
8 
16 
3.3.2. Vector Register Grouping (vlmul
)
Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers. Vector register groups allow doublewidth or larger elements to be operated on with the same vector length as standardwidth elements. Vector register groups also provide greater execution efficiency for longer application vectors.
The term vector register group is used herein to refer to one or
more vector registers used as a single operand to a vector
instruction. The number of vector registers in a group, LMUL, is an
integer power of two set by the vlmul
field in vtype
(LMUL =
2^{vlmul[1:0]}).
The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings.
vlmul  LMUL  #groups  VLMAX  Grouped registers  

0 
0 
1 
32 
VLEN/SEW 
vn (single register in group) 
0 
1 
2 
16 
2*VLEN/SEW 
vn, vn+1 
1 
0 
4 
8 
4*VLEN/SEW 
vn, …, vn+3 
1 
1 
8 
4 
8*VLEN/SEW 
vn, …, vn+7 
When vlmul=01
, then vector operations on register v
n also
operate on vector register v
n+1, giving twice the vector length
in bits. Instructions specifying a vector operand with an
oddnumbered vector register will raise an illegal instruction
exception.
Similarly, when vlmul=10
, vector instructions operate on four
vector registers at a time, and instructions specifying vector
operands using vector register numbers that are not multiples of four
will raise an illegal instruction exception. When vlmul=11
,
operations operate on eight vector registers at a time, and
instructions specifying vector operands using register numbers that
are not multiples of eight will raise an illegal instruction
exception.
Note

This grouping pattern (LMUL=8 has groups v0 ,v8 ,v16 ,v24 )
was adopted in 0.6 initially to avoid issues with the floatingpoint
calling convention when floatingpoint values were overlaid on the
vector registers, whereas earlier versions kept the vector register
group names contiguous (LMUL=8 has groups v0 , v1 , v2 , v3 ). In
versions v0.7 onwards, the floatingpoint registers are separate again.

Mask register instructions always operate on a single vector register, regardless of LMUL setting.
3.3.3. Vector Type Illegal vill
The vill
bit is used to encode that a previous vsetvl{i}
instruction attempted to write an unsupported value to vtype
.
Note

The vill bit is held in bit XLEN1 of the CSR to support
checking for illegal values with a branch on the sign bit.

If the vill
bit is set, then any attempt to execute a vector
instruction (other than a vector configuration instruction) will raise
an illegal instruction exception.
When the vill
bit is set, the other XLEN1 bits in vtype
shall be
zero.
3.4. Vector Length Register vl
The XLENbitwide readonly vl
CSR can only be updated by the
vsetvli
and vsetvl
instructions, and the faultonlyfirst vector load
instruction variants.
The vl
register holds an unsigned integer specifying the number of
elements to be updated by a vector instruction. Elements in any
destination vector register group with indices ≥ vl
are unmodified during
execution of a vector instruction. When vstart
≥ vl
,
no elements are updated in any destination vector register group.
Note

As a consequence, when vl =0, no elements are updated in the
destination vector register group, regardless of vstart .

Note

Instructions that write a scalar integer or floatingpoint register
do so even when vstart ≥ vl .

Note

The number of bits implemented in vl depends on the
implementation’s maximum vector length of the smallest supported
type. The smallest vector implementation, RV32IV, would need at least
six bits in vl to hold the values 032 (with VLEN=32, LMUL=8 and
SEW=8 results in VLMAX of 32).

3.5. Vector Byte Length vlenb
The XLENbitwide readonly CSR vlenb
holds the value VLEN/8,
i.e., the vector register length in bytes.
Note

The value in vlenb is a designtime constant in any
implementation.

Note

Without this CSR, several instructions are needed to calculate
VLEN in bytes. The code has to disturb current vl and vtype
settings which require them to be saved and restored.

3.6. Vector Start Index CSR vstart
The vstart
readwrite CSR specifies the index of the first element
to be executed by a vector instruction.
Normally, vstart
is only written by hardware on a trap on a vector
instruction, with the vstart
value representing the element on which
the trap was taken (either a synchronous exception or an asynchronous
interrupt), and at which execution should resume after a resumable
trap is handled.
All vector instructions are defined to begin execution with the
element number given in the vstart
CSR, leaving earlier elements in
the destination vector undisturbed, and to reset the vstart
CSR to
zero at the end of execution.
Note

All vector instructions, including vsetvl{i} , reset the vstart
CSR to zero.

vstart
is not modified by vector instructions that raise illegalinstruction
exceptions.
If the value in the vstart
register is greater than or equal to the
vector length vl
then no element operations are performed. The
vstart
register is then reset to zero.
The vstart
CSR is defined to have only enough writable bits to hold
the largest element index (one less than the maximum VLMAX) or
lg2(VLEN) bits. The upper bits of the vstart
CSR are hardwired to
zero (reads zero, writes ignored).
Note

The maximum vector length is obtained with the largest LMUL
setting (8) and the smallest SEW setting (8), so VLMAX_max = 8*VLEN/8
= VLEN. For example, for VLEN=256, vstart would have 8 bits to
represent indices from 0 through 255.

The vstart
CSR is writable by unprivileged code, but nonzero
vstart
values may cause vector instructions to run substantially
slower on some implementations, so vstart
should not be used by
application programmers. A few vector instructions cannot be
executed with a nonzero vstart
value and will raise an illegal
instruction exception as defined below.
Note

Making vstart visible to unprivileged code supports userlevel
threading libraries.

Implementations are permitted to raise illegal instruction exceptions when
attempting to execute a vector instruction with a value of vstart
that the
implementation can never produce when executing that same instruction with
the same vtype
setting.
Note

For example, some implementations will never take interrupts during
execution of a vector arithmetic instruction, instead waiting until the
instruction completes to take the interrupt. Such implementations are
permitted to raise an illegal instruction exception when attempting to execute
a vector arithmetic instruction when vstart is nonzero.

3.7. Vector FixedPoint Rounding Mode Register vxrm
The vector fixedpoint roundingmode register holds a twobit
readwrite roundingmode field. The vector fixedpoint roundingmode
is given a separate CSR address to allow independent access, but is
also reflected as a field in the upper bits of fcsr
. Systems
without floatingpoint must add fcsr
when adding the vector
extension.
The fixedpoint rounding algorithm is specified as follows.
Suppose the prerounding result is v
, and d
bits of that result are to be
rounded off.
Then the rounded result is (v >> d) + r
, where r
depends on the rounding
mode as specified in the following table.
Bits [1:0]  Abbreviation  Rounding Mode  Rounding increment, r 


0 
0 
rnu 
roundtonearestup (add +0.5 LSB) 

0 
1 
rne 
roundtonearesteven 

1 
0 
rdn 
rounddown (truncate) 

1 
1 
rod 
roundtoodd (OR bits into LSB, aka "jam") 

The rounding functions:
roundoff_unsigned(v, d) = (unsigned(v) >> d) + r roundoff_signed(v, d) = (signed(v) >> d) + r
are used to represent this operation in the instruction descriptions below.
Bits[XLEN1:2] should be written as zeros.
Note

The rounding mode can be set with a single csrwi instruction.

3.8. Vector FixedPoint Saturation Flag vxsat
The vxsat
CSR holds a single readwrite bit that indicates if a
fixedpoint instruction has had to saturate an output value to fit
into a destination format.
The vxsat
bit is mirrored in the upper bits of fcsr
.
3.9. Vector FixedPoint Fields in fcsr
The vxrm
and vxsat
separate CSRs can also be accessed via fields
in the floatingpoint CSR, fcsr
. The fcsr
register must be added
to systems without floatingpoint that add a vector extension.
Bits  Name  Description 

10:9 
vxrm 
Fixedpoint rounding mode 
8 
vxsat 
Fixedpoint accrued saturation flag 
7:5 
frm 
Floatingpoint rounding mode 
4:0 
fflags 
Floatingpoint accrued exception flags 
Note

The fields are packed into fcsr to make contextsave/restore
faster.

3.10. State of Vector Extension at Reset
The vector extension must have a consistent state at reset. In
particular, vtype
and vl
must have values that can be read and
then restored with a single vsetvl
instruction.
Note

It is recommended that at reset, vtype.vill is set, the
remaining bits in vtype are zero, and vl is set to zero.

The vstart
, vxrm
, vxsat
CSRs can have arbitrary values at reset.
Note

Any use of the vector unit will require an initial vsetvl{i} ,
which will reset vstart . The vxrm and vxsat fields should be
reset explicitly in software before use.

The vector registers can have arbitrary values at reset.
4. Mapping of Vector Elements to Vector Register State
The following diagrams illustrate how different width elements are packed into the bytes of a vector register depending on the current SEW and LMUL settings, as well as implementation ELEN and VLEN. Elements are packed into each vector register with the leastsignificant byte in the lowestnumbered bits.
Note

Previous RISCV vector proposals (< 0.6) hid this mapping from
software, whereas this proposal has a specific mapping for all
configurations, which reduces implementation flexibility but removes
need for zeroing on config changes. Making the mapping explicit also
has the advantage of simplifying oblivious context saverestore code,
as the code can save the configuration in vl and vtype ,
then reset vtype to a convenient value (e.g., four vector groups of
LMUL=8, SEW=ELEN) before saving all vector register bits without
needing to parse the configuration. The reverse process will restore
the state.

4.1. Mapping with LMUL=1
When LMUL=1, elements are simply packed in order from the leastsignificant to mostsignificant bits of the vector register.
Note

To increase readability, vector register layouts are drawn with bytes ordered from right to left with increasing byte address. Bits within an element are numbered in a littleendian format with increasing bit index from right to left corresponding to increasing magnitude. 
The element index is given in hexadecimal and is shown placed at the leastsignificant byte of the stored element. ELEN <=128 and LMUL=1 throughout. VLEN=32b Byte 3 2 1 0 SEW=8b 3 2 1 0 SEW=16b 1 0 SEW=32b 0 VLEN=64b Byte 7 6 5 4 3 2 1 0 SEW=8b 7 6 5 4 3 2 1 0 SEW=16b 3 2 1 0 SEW=32b 1 0 SEW=64b 0 VLEN=128b Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b 7 6 5 4 3 2 1 0 SEW=32b 3 2 1 0 SEW=64b 1 0 SEW=128b 0 VLEN=256b Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=32b 7 6 5 4 3 2 1 0 SEW=64b 3 2 1 0 SEW=128b 1 0
4.2. Mapping with LMUL > 1
When vector registers are grouped, the elements of the vector register group are striped across the constituent vector registers. The striping distance in bits, SLEN, sets how many bits are packed contiguously into one vector register before moving to the next in the group.
For example, when SLEN = 128, the striping pattern is repeated in multiples of 128 bits. The first 128/SEW elements are packed contiguously at the start of the first vector register in the group. The next 128/SEW elements are packed contiguously at the start of the next vector register in the group. After packing the first LMUL*128/SEW elements at the start of each of the LMUL vector registers in the group, the second LMUL*128/SEW group of elements are packed into the second 128b segment of each of the vector registers in the group, and so on.
Example 1: VLEN=32b, SEW=16b, LMUL=2 Byte 3 2 1 0 v2*n 1 0 v2*n+1 3 2 Example 2: VLEN=64b, SEW=32b, LMUL=2 Byte 7 6 5 4 3 2 1 0 v2*n 1 0 v2*n+1 3 2 Example 3: VLEN=128b, SEW=32b, LMUL=2 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4 Example 4: VLEN=256b, SEW=32b, LMUL=2 Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n B A 9 8 3 2 1 0 v2*n+1 F E D C 7 6 5 4
If SEW > SLEN, the striping pattern places one element in each vector register in the group before moving to the next vector register in the group. So, when LMUL=2, the evennumbered vector register contains the evennumbered elements of the vector and the oddnumbered vector register contains the oddnumbered elements of the vector.
Note

In most implementations, the striping distance SLEN ≥ ELEN. 
Example: VLEN=256b, SEW=256b, LMUL=2 Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 0 v2*n+1 1
When LMUL = 4, four vector registers hold elements as shown:
Example 1: VLEN=32b, SLEN=32b, SEW=16b, LMUL=4, Byte 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 Example 2: VLEN=64b, SLEN=64b, SEW=32b, LMUL=4 Byte 7 6 5 4 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 Example 3: VLEN=128b, SLEN=64b, SEW=32b, LMUL=4 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 9 8 1 0 32b elements v4*n+1 B A 3 2 v4*n+2 D C 5 4 v4*n+3 F E 7 6 Example 4: VLEN=128b, SLEN=128b, SEW=32b, LMUL=4 Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 3 2 1 0 32b elements v4*n+1 7 6 5 4 v4*n+2 B A 9 8 v4*n+3 F E D C Example 5: VLEN=256b, SLEN=128b, SEW=32b, LMUL=4 Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 13 12 11 10 3 2 1 0 v4*n+1 17 16 15 14 7 6 5 4 v4*n+2 1B 1A 19 18 B A 9 8 v4*n+3 1F 1E 1D 1C F E D C Example 6: VLEN=256b, SLEN=128b, SEW=256b, LMUL=4 Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 0 v4*n+1 1 v4*n+2 2 v4*n+3 3
A similar pattern is followed for LMUL = 8.
Example: VLEN=256b, SLEN=128b, SEW=32b, LMUL=8 Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 v8*n 23 22 21 20 3 2 1 0 v8*n+1 27 26 25 24 7 6 5 4 v8*n+2 2B 2A 29 28 B A 9 8 v8*n+3 2F 2E 2D 2C F E D C v8*n+4 33 32 31 30 13 12 11 10 v8*n+5 37 36 35 34 17 16 15 14 v8*n+6 3B 3A 39 38 1B 1A 19 18 v8*n+7 3F 3E 3D 3C 1F 1E 1D 1C
Different striping patterns are architecturally visible, but software can be written that produces the same results regardless of striping pattern. The primary constraint is to not change the LMUL used to access values held in a vector register group (i.e., do not read values with a different LMUL than used to write values to the group).
Note

The striping length SLEN for an implementation is set to optimize the tradeoff between datapath wiring for mixedwidth operations and buffering needed to cornerturn wide vector unitstride memory accesses into parallel accesses for the vector register file. 
Note

The previous explicit configuration design (version < 0.6) allowed these tradeoffs to be managed at the microarchitectural level and optimized for each configuration. 
4.3. Mapping across MixedWidth Operations
The pattern used to map elements within a vector register group is
designed to reduce datapath wiring when supporting operations across
multiple element widths. The recommended software strategy in this
case is to modify vtype
dynamically to keep SEW/LMUL constant (and
hence VLMAX constant).
The following example shows four different packed element widths (8b, 16b, 32b, 64b) in a VLEN=256b/SLEN=128b implementation. The vector register grouping factor (LMUL) is increased by the relative element size such that each group can hold the same number of vector elements (32 in this example) to simplify stripmining code. Any operation between elements with the same index only touches operand bits located within the same 128b portion of the datapath.
VLEN=256b, SLEN=128b Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1, VLMAX=32 v1 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b, LMUL=2, VLMAX=32 v2*n 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 v2*n+1 1F 1E 1D 1C 1B 1A 19 18 F E D C B A 9 8 SEW=32b, LMUL=4, VLMAX=32 v4*n 13 12 11 10 3 2 1 0 v4*n+1 17 16 15 14 7 6 5 4 v4*n+2 1B 1A 19 18 B A 9 8 v4*n+3 1F 1E 1D 1C F E D C SEW=64b, LMUL=8, VLMAX=32 v8*n 11 10 1 0 v8*n+1 13 12 3 2 v8*n+2 15 14 5 4 v8*n+3 17 16 7 6 v8*n+4 19 18 9 8 v8*n+5 1B 1A B A v8*n+6 1D 1C D C v8*n+7 1F 1E F E
Larger LMUL settings can also used to simply increase vector length to reduce instruction fetch and dispatch overheads, in cases where fewer logical vector registers are required.
The following table shows each possible constant SEW/LMUL operating point for loops with mixedwidth operations.
Numbers in columns are LMUL values, and each column represents constant SEW/LMUL operating point SEW/LMUL 1 2 4 8 16 32 64 128 256 512 1024 SEW 8 8 4 2 1 16 8 4 2 1 32 8 4 2 1 64 8 4 2 1 128 8 4 2 1 256 8 4 2 1 512 8 4 2 1 1024 8 4 2 1
Note

Larger LMUL values can cause lower datapath utilization for
short vectors if SLEN is less than the spatial datapath width. In the
example above with VLEN=256b, SLEN=128b, and LMUL=8, if the
implementation is purely spatial with a 256bwide vector datapath,
then for an application vector length less than 17, only half of the
datapath will be active. The vsetvl instructions below could have a
facility added to dynamically select an appropriate LMUL according to
the required application vector length (AVL) and range of element
widths.

Note

Narrower machines will set SLEN to be at least as large as the datapath spatial width, so there is no need to reduce LMUL. Wider machines might set SLEN lower than the spatial datapath width to reduce wiring for mixedwidth operations (e.g., width=1024, ELEN=32, SLEN=128), in which case optimizing LMUL will be important. 
4.4. Mask Register Layout
A vector mask occupies only one vector register regardless of SEW and LMUL. The mask bits that are used for each vector operation depends on the current SEW and LMUL setting.
The maximum number of elements in a vector operand is:
VLMAX = LMUL * VLEN/SEW
A mask is allocated for each element by dividing the mask register into VLEN/VLMAX fields. The size of each mask element in bits, MLEN, is:
MLEN = VLEN/VLMAX = VLEN/(LMUL * VLEN/SEW) = SEW/LMUL
The size of MLEN varies from ELEN (SEW=ELEN, LMUL=1) down to 1 (SEW=8b,LMUL=8), and hence a single vector register can always hold the entire mask register.
The mask bits for element i are located in bits [MLEN*i+(MLEN1) : MLEN*i] of the mask register. When a mask element is written by a compare instruction, the low bit in the mask element is written with the compare result and the upper bits of the mask element are zeroed. Destination mask elements past the end of the current vector length are unchanged. When a value is read as a mask, only the leastsignificant bit of the mask element is used to control masking and the upper bits are ignored.
The pattern is such that for constant SEW/LMUL values, the effective predicate bits are located in the same bit of the mask vector register, which simplifies use of masking in loops with mixedwidth elements.
VLEN=32b Byte 3 2 1 0 LMUL=1,SEW=8b 3 2 1 0 Element [24][16][08][00] Mask bit position in decimal LMUL=2,SEW=16b 1 0 [08] [00] 3 2 [24] [16] LMUL=4,SEW=32b 0 [00] 1 [08] 2 [16] 3 [24]
LMUL=2,SEW=8b 3 2 1 0 [12][08][04][00] 7 6 5 4 [28][24][20][16] LMUL=8,SEW=32b 0 [00] 1 [04] 2 [08] 3 [12] 4 [16] 5 [20] 6 [24] 7 [28] LMUL=8,SEW=8b 3 2 1 0 [03][02][01][00] 7 6 5 4 [07][06][05][04] B A 9 8 [11][10][09][08] F E D C [15][14][13][12] 13 12 11 10 [19][18][17][16] 17 16 15 14 [23][22][21][20] 1B 1A 19 18 [27][26][25][24] 1F 1E 1D 1C [31][30][29][28]
VLEN=256b, SLEN=128b Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1, VLMAX=32 v1 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 [248] ... [128] ...[96] ...[64] ...[32] ... [0] Mask bit positions in decimal SEW=16b, LMUL=2, VLMAX=32 v2*n 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 [184] ... [128] ... [32] ... [0] v2*n+1 1F 1E 1D 1C 1B 1A 19 18 F E D C B A 9 8 [248] ... [196] ... [96] ... [64] SEW=32b, LMUL=4, VLMAX=32 v4*n 13 12 11 10 3 2 1 0 [152] ... [128] [24] ... [0] v4*n+1 17 16 15 14 7 6 5 4 [184] ... [160] [56] ... [32] v4*n+2 1B 1A 19 18 B A 9 8 [116] ... [192] [88] ... [64] v4*n+3 1F 1E 1D 1C F E D C [248] ... [224] [120] ... [96] SEW=64b, LMUL=8, VLMAX=32 v8*n 11 10 1 0 [136] [128] [8] [0] v8*n+1 13 12 3 2 [152] [144] [24] [16] v8*n+2 15 14 5 4 [168] [160] [40] [32] v8*n+3 17 16 7 6 [184] [176] [56] [48] v8*n+4 19 18 9 8 [200] [192] [72] [64] v8*n+5 1B 1A B A [216] [208] [88] [80] v8*n+6 1D 1C D C [232] [224] [104] [96] v8*n+7 1F 1E F E [248] [240] [120] [112]
5. Vector Instruction Formats
The instructions in the vector extension fit under three existing major opcodes (LOADFP, STOREFP, AMO) and one new major opcode (OPV).
Vector loads and stores are encoding within the scalar floatingpoint load and store major opcodes (LOADFP/STOREFP). The vector load and store encodings repurpose a portion of the standard scalar floatingpoint load/store 12bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see Mask Encoding).
Format for Vector Load Instructions under LOADFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  mop  vm  lumop  rs1  width  vd 0000111 VL* unitstride nf  mop  vm  rs2  rs1  width  vd 0000111 VLS* strided nf  mop  vm  vs2  rs1  width  vd 0000111 VLX* indexed 3 3 1 5 5 3 5 7 Format for Vector Store Instructions under STOREFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  mop  vm  sumop  rs1  width  vs3 0100111 VS* unitstride nf  mop  vm  rs2  rs1  width  vs3 0100111 VSS* strided nf  mop  vm  vs2  rs1  width  vs3 0100111 VSX* indexed 3 3 1 5 5 3 5 7
Format for Vector AMO Instructions under AMO major opcode 31 27 26 25 24 20 19 15 14 12 11 7 6 0 amoop wd vm  vs2  rs1  width  vs3/vd 0101111 VAMO* 5 1 1 5 5 3 5 7
Formats for Vector Arithmetic Instructions under OPV major opcode 31 26 25 24 20 19 15 14 12 11 7 6 0 funct6  vm  vs2  vs1  0 0 0  vd 1010111 OPV (OPIVV) funct6  vm  vs2  vs1  0 0 1  vd/rd 1010111 OPV (OPFVV) funct6  vm  vs2  vs1  0 1 0  vd/rd 1010111 OPV (OPMVV) funct6  vm  vs2  simm5  0 1 1  vd 1010111 OPV (OPIVI) funct6  vm  vs2  rs1  1 0 0  vd 1010111 OPV (OPIVX) funct6  vm  vs2  rs1  1 0 1  vd 1010111 OPV (OPFVF) funct6  vm  vs2  rs1  1 1 0  vd/rd 1010111 OPV (OPMVX) 6 1 5 5 3 5 7
Formats for Vector Configuration Instructions under OPV major opcode 31 30 25 24 20 19 15 14 12 11 7 6 0 0  zimm[10:0]  rs1  1 1 1  rd 1010111 vsetvli 1  000000  rs2  rs1  1 1 1  rd 1010111 vsetvl 1 6 5 5 3 5 7
Vector instructions can have scalar or vector source operands and produce scalar or vector results, and most vector instructions can be performed either unconditionally or conditionally under a mask.
Vector loads and stores move bit patterns between vector register elements and memory. Vector arithmetic instructions operate on values held in vector register elements.
5.1. Scalar Operands
Scalar operands can be immediates, or taken from the x
registers,
the f
registers, or element 0 of a vector register. Scalar results
are written to an x
or f
register or to element 0 of a vector
register. Any vector register can be used to hold a scalar regardless
of the current LMUL setting.
Note

In a change from v0.6, the floatingpoint registers no longer
overlay the vector registers and scalars can now come from the integer
or floatingpoint registers. Not overlaying the f registers reduces
vector register pressure, avoids interactions with the standard
calling convention, simplifies highperformance scalar floatingpoint
design, and provides compatibility with the Zfinx ISA option.
Overlaying f with v would provide the advantage of lowering the
number of state bits in some implementations, but complicates
highperformance designs and would prevent compatibility with the
Zfinx ISA option.

5.2. Vector Operands
Vector operands or results may occupy one or more vector registers depending on LMUL, but are always specified using the lowestnumbered vector register in the group. Using other than the lowestnumbered vector register to specify a vector register group will result in an illegal instruction exception.
Some vector instructions consume and produce widerwidth elements and
so operate on a larger vector register group than that specified in
vlmul
. The largest vector register group used by an instruction can
not be greater than 8 vector registers, and if an vector instruction
would require greater than 8 vector registers in a group, an illegal
instruction exception is raised. For example, attempting a widening
operation producing a widened vector register group result with LMUL=8
will raise an illegal instruction exception. Widened scalar values,
e..g, results from widening reduction operations, are held in the
first element of a vector register and are treated as if LMUL=1.
5.3. Vector Masking
Masking is supported on many vector instructions. Element operations that are masked off do not modify the destination vector register element and never generate exceptions.
In the base vector extension, the mask value used to control execution
of a masked vector instruction is always supplied by vector register
v0
. Only the leastsignificant bit of each element of the mask
vector is used to control execution.
Note

Future vector extensions may provide longer instruction encodings with space for a full mask register specifier. 
The destination vector register group for a masked vector instruction
can only overlap the source mask register (v0
) when
LMUL=1. Otherwise, an illegal instruction exception is raised.
Note

This constraint supports restart with a nonzero vstart value.

Other vector registers can be used to hold working mask values, and mask vector logical operations are provided to perform predicate calculations.
5.3.1. Mask Encoding
Where available, masking is encoded in a singlebit vm
field in the
instruction (inst[25]
).
vm  Description 

0 
vector result, only where v0[i].LSB = 1 
1 
unmasked 
Note

In earlier proposals, vm was a twobit field vm[1:0] that
provided both true and complement masking using v0 as well as
encoding scalar operations.

Vector masking is represented in assembler code as another vector
operand, with .t
indicating if operation occurs when v0[i].LSB
is
1
. If no masking operand is specified, unmasked vector execution
(vm=1
) is assumed.
vop.v* v1, v2, v3, v0.t # enabled where v0[i].LSB=1, m=0 vop.v* v1, v2, v3 # unmasked vector operation, m=1
Note

Even though the base only supports one vector mask register v0
and only the true form of predication, the assembly syntax writes it
out in full to be compatible with future extensions that might add a
mask register specifier and supporting both true and complement
masking. The .t suffix on the masking operand also helps to visually
encode the use of a mask.

5.4. Prestart, Active, Inactive, Body, and Tail Element Definitions
The elements operated on during a vector instruction’s execution can be divided into four disjoint subsets.

The prestart elements are those whose element index is less than the initial value in the
vstart
register. The prestart elements do not raise exceptions and do not update the destination vector register. 
The active elements during a vector instruction’s execution are the elements within the current vector length setting and where the current mask is enabled at that element position. The active elements can raise exceptions and update the destination vector register group.

The inactive elements are the elements within the current vector length setting but where the current mask is disabled at that element position. The inactive elements do not raise exceptions and do not update any destination vector register.

The tail elements during a vector instruction’s execution are the elements past the current vector length setting. The tail elements do not raise exceptions, and do not update any destination vector register group.

In addition, another term, body, is used for the set of elements that are either active or inactive, i.e., after prestart but before the tail.
for element index x prestart = (0 <= x < vstart) mask(x) = unmasked  v0[x].LSB == 1 active(x) = (vstart <= x < vl) && mask(x) inactive(x) = (vstart <= x < vl) && !mask(x) body(x) = active(x)  inactive(x) tail(x) = (vl <= x < VLMAX)
Note

The inactive and tail update rules leave unchanged destination elements that are not participating in the vector operation. Previous versions (v0.7) of the specification zeros the tail elements to reduce the complexity of implementations that implement register renaming. In version 0.8, this was changed to leave the tail elements undisturbed, which reduces complexity for simpler implementations without register renaming and reduces software overhead for some common sequences. A rationale is provided in a separate document: https://github.com/riscv/riscvvspec/blob/master/vundisturbedversuszeroing.adoc 
6. ConfigurationSetting Instructions
A set of instructions are provided to allow rapid configuration of the
values in vl
and vtype
to match application needs.
6.1. vsetvli
/vsetvl
instructions
The vsetvli
instruction sets the vtype
and vl
CSRs based on its
arguments, and writes the new value of vl
into rd
.
vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value
The new vtype
setting is encoded in the immediate fields of
vsetvli
and in the rs2
register for vsetvl
. The new vector
length setting is based on the requested application vector length
(AVL), which is encoded in the rs1
and rd
fields as follows:


AVL value 
Description/Usage 
0 
0 
Value in 
Change 
!0 
0 
~0 
Set 
 
!0 
Value in 
Normal stripmining 
When rs1
is not x0
, the AVL is an unsigned integer held in the x
register specified by rs1
, and the new vl
value is also written to
the x
register specified by rd
.
When rs1=x0
but rd!=x0
, the maximum unsigned integer value (~0
)
is used as the AVL, and the resulting VLMAX is written to vl
and
also to the x
register specified by rd
.
When rs1=x0
and rd=x0
, the current vector length in vl
is used
as the AVL, and the resulting value is only written to vl
.
Note

This form of the instruction allows the vtype register to be
changed without changing vl , provided VLMAX is not reduced. The
current vl value can be read from the vl CSR.

Formats for Vector Configuration Instructions under OPV major opcode 31 30 25 24 20 19 15 14 12 11 7 6 0 0  zimm[10:0]  rs1  1 1 1  rd 1010111 vsetvli 1  000000  rs2  rs1  1 1 1  rd 1010111 vsetvl 1 6 5 5 3 5 7
Bits  Name  Description 

XLEN1 
vill 
Illegal value if set 
XLEN2:7 
Reserved (write 0) 

6:5 
vediv[1:0] 
Used by EDIV extension 
4:2 
vsew[2:0] 
Standard element width (SEW) setting 
1:0 
vlmul[1:0] 
Vector register group multiplier (LMUL) setting 
Suggested assembler names used for vtypei setting e8 # 8b elements e16 # 16b elements e32 # 32b elements e64 # 64b elements e128 # 128b elements m1 # Vlmul x1, assumed if m setting absent m2 # Vlmul x2 m4 # Vlmul x4 m8 # Vlmul x8 d1 # EDIV 1, assumed if d setting absent d2 # EDIV 2 d4 # EDIV 4 d8 # EDIV 8 Examples: vsetvli t0, a0, e8 # SEW= 8, LMUL=1, EDIV=1 vsetvli t0, a0, e8,m2 # SEW= 8, LMUL=2, EDIV=1 vsetvli t0, a0, e32,m2,d4 # SEW=32, LMUL=2, EDIV=4
If the vtype
setting is not supported by the implementation, then
the vill
bit is set in vtype
, the remaining bits in vtype
are
set to zero, and the vl
register is also set to zero.
Note

Earlier drafts required a trap when setting vtype to an
illegal value. However, this would have added the first
datadependent trap on a CSR write to the ISA. The current scheme
also supports lightweight runtime interrogation of the supported
vector unit configurations by checking if vill is clear for a given
setting.

6.2. Constraints on Setting vl
The vsetvl{i}
instructions first set VLMAX according to the vtype
argument, then set vl
obeying the following constraints:

vl = AVL
ifAVL ≤ VLMAX

ceil(AVL / 2) ≤ vl ≤ VLMAX
ifAVL < (2 * VLMAX)

vl = VLMAX
ifAVL ≥ (2 * VLMAX)

Deterministic on any given implementation for same input AVL and VLMAX values

These specific properties follow from the prior rules:

vl = 0
ifAVL = 0

vl > 0
ifAVL > 0

vl ≤ VLMAX

vl ≤ AVL

a value read from
vl
when used as the AVL argument tovsetvl{i}
results in the same value invl
, provided the resultant VLMAX equals the value of VLMAX at the time thatvl
was read

Note

The For example, this permits an implementation to set 
6.3. vsetvl
Instruction
The vsetvl
variant operates similarly to vsetvli
except that it
takes a vtype
value from rs2
and can be used for context restore,
and when the vtypei
field is too small to hold the desired setting.
Note

Several active complex types can be held in different x
registers and swapped in as needed using vsetvl .

6.4. Examples
The SEW and LMUL settings can be changed dynamically to provide high throughput on mixedwidth operations in a single loop.
# Example: Load 16bit values, widen multiply to 32b, shift 32b result # right by 3, store 32b values. # Loop using only widest elements: loop: vsetvli a3, a0, e32,m8 # Use only 32bit elements vlh.v v8, (a1) # Signextend 16b load values to 32b elements sll t1, a3, 1 # Multiply length by two bytes/element add a1, a1, t1 # Bump pointer vmul.vx v8, v8, x10 # 32b multiply result vsrl.vi v8, v8, 3 # Shift elements vsw.v v8, (a2) # Store vector of 32b results sll t1, a3, 2 # Multiply length by four bytes/element add a2, a2, t1 # Bump pointer sub a0, a0, a3 # Decrement count bnez a0, loop # Any more? # Alternative loop that switches element widths. loop: vsetvli a3, a0, e16,m4 # vtype = 16bit integer vectors vlh.v v4, (a1) # Get 16b vector slli t1, a3, 1 # Multiply length by two bytes/element add a1, a1, t1 # Bump pointer vwmul.vx v8, v4, x10 # 32b in <v8v15> vsetvli x0, a0, e32,m8 # Operate on 32b values vsrl.vi v8, v8, 3 vsw.v v8, (a2) # Store vector of 32b slli t1, a3, 2 # Multiply length by four bytes/element add a2, a2, t1 # Bump pointer sub a0, a0, a3 # Decrement count bnez a0, loop # Any more?
The second loop is more complex but will have greater performance on machines where 16b widening multiplies are faster than 32b integer multiplies, and where 16b vector load can run faster due to the narrower writes to the vector regfile.
7. Vector Loads and Stores
Vector loads and stores move values between vector registers and memory. Vector loads and stores are masked and do not raise exceptions on inactive elements. Masked vector loads do not update inactive elements in the destination vector register group. Masked vector stores only update active memory elements.
7.1. Vector Load/Store Instruction Encoding
Vector loads and stores are encoded within the scalar floatingpoint load and store major opcodes (LOADFP/STOREFP). The vector load and store encodings repurpose a portion of the standard scalar floatingpoint load/store 12bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see Mask Encoding).
Format for Vector Load Instructions under LOADFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  mop  vm  lumop  rs1  width  vd 0000111 VL* unitstride nf  mop  vm  rs2  rs1  width  vd 0000111 VLS* strided nf  mop  vm  vs2  rs1  width  vd 0000111 VLX* indexed 3 3 1 5 5 3 5 7 Format for Vector Store Instructions under STOREFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  mop  vm  sumop  rs1  width  vs3 0100111 VS* unitstride nf  mop  vm  rs2  rs1  width  vs3 0100111 VSS* strided nf  mop  vm  vs2  rs1  width  vs3 0100111 VSX* indexed 3 3 1 5 5 3 5 7
Field  Description 

rs1[4:0] 
specifies x register holding base address 
rs2[4:0] 
specifies x register holding stride 
vs2[4:0] 
specifies v register holding address offsets 
vs3[4:0] 
specifies v register holding store data 
vd[4:0] 
specifies v register destination of load 
vm 
specifies vector mask 
width[2:0] 
specifies size of memory elements, and distinguishes from FP scalar 
mop[2:0] 
specifies memory addressing mode 
nf[2:0] 
specifies the number of fields in each segment, for segment load/stores 
lumop[4:0]/sumop[4:0] 
are additional fields encoding variants of unitstride instructions 
7.2. Vector Load/Store Addressing Modes
The base vector extension supports unitstride, strided, and
indexed (scatter/gather) addressing modes. Vector load/store base
registers and strides are taken from the GPR x
registers.
The base effective address for all vector accesses is given by the
contents of the x
register named in rs1
.
Vector unitstride operations access elements stored contiguously in memory starting from the base effective address.
Vector strided operations access the first memory element at the base
effective address, and then access subsequent elements at address
increments given by the byte offset contained in the x
register
specified by rs2
.
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2
to the base effective address
to give the effective address of each element. The vector offset
operand is treated as a vector of byte offsets. If the vector offset
elements are narrower than XLEN, they are zeroextended to XLEN before
adding to the base effective address. If the vector offset elements
are wider than XLEN, the leastsignificant XLEN bits are used in the
address calculation.
Note

Current PoR for vector indexed instructions requires that vector byte offset (vs2) and vector read/write data (vs3/vd) are of same width. One question is whether and how to allow for two sizes of vector operand in a vector indexed instruction? For example, for scatter/gather of byte values in a 64bit address space without requiring bytes use 64b of space in a vector register. 
The vector addressing modes are encoded using the 3bit mop[2:0]
field.
mop [2:0]  Description  Opcodes  

0 
0 
0 
zeroextended unitstride 
VLxU,VLE 
0 
0 
1 
reserved 

0 
1 
0 
zeroextended strided 
VLSxU, VLSE 
0 
1 
1 
zeroextended indexed 
VLXxU, VLXE 
1 
0 
0 
signextended unitstride 
VLx (x!=E) 
1 
0 
1 
reserved 

1 
1 
0 
signextended strided 
VLSx (x!=E) 
1 
1 
1 
signextended indexed 
VLXx (x!=E) 
mop [2:0]  Description  Opcodes  

0 
0 
0 
unitstride 
VSx 
0 
0 
1 
reserved 

0 
1 
0 
strided 
VSSx 
0 
1 
1 
indexedordered 
VSXx 
1 
0 
0 
reserved 

1 
0 
1 
reserved 

1 
1 
0 
reserved 

1 
1 
1 
indexedunordered 
VSUXx 
The vector indexed memory operations have two forms, ordered and unordered. The indexedunordered stores do not preserve element ordering on stores.
Note

The indexedunordered variant is provided as a potential implementation optimization. Implementations are free to ignore the optimization and implement indexedunordered identically to indexedordered. 
Additional unitstride vector addressing modes are encoded using the
5bit lumop
and sumop
fields in the unitstride load and store
instruction encodings respectively.
lumop[4:0]  Description  

0 
0 
0 
0 
0 
unitstride 
0 
0 
x 
x 
x 
reserved, x !=0 
0 
1 
0 
0 
0 
unitstride, whole registers 
0 
1 
x 
x 
x 
reserved, x !=0 
1 
0 
0 
0 
0 
unitstride faultonlyfirst 
1 
x 
x 
x 
x 
reserved, x!=0 
sumop[4:0]  Description  

0 
0 
0 
0 
0 
unitstride 
0 
0 
x 
x 
x 
reserved, x !=0 
0 
1 
0 
0 
0 
unitstride, whole registers 
0 
1 
x 
x 
x 
reserved, x !=0 
1 
x 
x 
x 
x 
reserved 
The nf[2:0]
field encodes the number of fields in each segment. For
regular vector loads and stores, nf
=0, indicating that a single
value is moved between a vector register group and memory at each
element position. Larger values in the nf
field are used to access
multiple contiguous fields within a segment as described below in
Section Vector Load/Store Segment Instructions (Zvlsseg
).
Note

The nf field for segment load/stores has replaced the use of
the same bits for an address offset field. The offset can be replaced
with a single scalar integer calculation, while segment load/stores
add more powerful primitives to move items to and from memory.

The nf[2:0]
field also encodes the number of whole vector registers
to transfer for the whole vector register load/store instructions.
7.3. Vector Load/Store Width Encoding
The vector loads and stores are encoded using the width values that are not claimed by the standard scalar floatingpoint loads and stores. Three of the width types encode vector loads and stores that move fixedsize memory elements of 8 bits, 16 bits, or 32 bits, while the fourth encoding moves SEWbit memory elements.
Width [2:0]  Mem bits  Reg bits  Opcode  

Standard scalar FP 
0 
0 
1 
16 
FLEN 
FLH/FSH 
Standard scalar FP 
0 
1 
0 
32 
FLEN 
FLW/FSW 
Standard scalar FP 
0 
1 
1 
64 
FLEN 
FLD/FSD 
Standard scalar FP 
1 
0 
0 
128 
FLEN 
FLQ/FSQ 
Vector byte 
0 
0 
0 
vl*8 
vl*SEW 
VxB 
Vector halfword 
1 
0 
1 
vl*16 
vl*SEW 
VxH 
Vector word 
1 
1 
0 
vl*32 
vl*SEW 
VxW 
Vector element 
1 
1 
1 
vl*SEW 
vl*SEW 
VxE 
Mem bits is the size of element accessed in memory
Reg bits is the size of element accessed in register
Fixedsized vector loads can optionally sign or zeroextend their memory element into the destination register element if the register element is wider than the memory element. A fixedsize vector load raises an illegal instruction exception if the destination register element is narrower than the memory element. The variablesized load is encoded as if a zeroextended load, with what would be the signextended encoding of a variablesized load currently reserved.
Fixedsize vector stores take their operand from the leastsignificant bits of the register element if the register element if wider than the memory element. Fixedsized vector stores raise an illegal instruction exception if the memory element is wider than the register element.
7.4. Vector UnitStride Instructions
# Vector unitstride loads and stores # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) vlb.v vd, (rs1), vm # 8b signed vlh.v vd, (rs1), vm # 16b signed vlw.v vd, (rs1), vm # 32b signed vlbu.v vd, (rs1), vm # 8b unsigned vlhu.v vd, (rs1), vm # 16b unsigned vlwu.v vd, (rs1), vm # 32b unsigned vle.v vd, (rs1), vm # SEW # vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>) vsb.v vs3, (rs1), vm # 8b store vsh.v vs3, (rs1), vm # 16b store vsw.v vs3, (rs1), vm # 32b store vse.v vs3, (rs1), vm # SEW store
7.5. Vector Strided Instructions
# Vector strided loads and stores # vd destination, rs1 base address, rs2 byte stride vlsb.v vd, (rs1), rs2, vm # 8b vlsh.v vd, (rs1), rs2, vm # 16b vlsw.v vd, (rs1), rs2, vm # 32b vlsbu.v vd, (rs1), rs2, vm # unsigned 8b vlshu.v vd, (rs1), rs2, vm # unsigned 16b vlswu.v vd, (rs1), rs2, vm # unsigned 32b vlse.v vd, (rs1), rs2, vm # SEW # vs3 store data, rs1 base address, rs2 byte stride vssb.v vs3, (rs1), rs2, vm # 8b vssh.v vs3, (rs1), rs2, vm # 16b vssw.v vs3, (rs1), rs2, vm # 32b vsse.v vs3, (rs1), rs2, vm # SEW
Note

Negative and zero strides are supported. 
7.6. Vector Indexed Instructions
# Vector indexed loads and stores # vd destination, rs1 base address, vs2 indices vlxb.v vd, (rs1), vs2, vm # 8b vlxh.v vd, (rs1), vs2, vm # 16b vlxw.v vd, (rs1), vs2, vm # 32b vlxbu.v vd, (rs1), vs2, vm # 8b unsigned vlxhu.v vd, (rs1), vs2, vm # 16b unsigned vlxwu.v vd, (rs1), vs2, vm # 32b unsigned vlxe.v vd, (rs1), vs2, vm # SEW # Vector orderedindexed store instructions # vs3 store data, rs1 base address, vs2 indices vsxb.v vs3, (rs1), vs2, vm # 8b vsxh.v vs3, (rs1), vs2, vm # 16b vsxw.v vs3, (rs1), vs2, vm # 32b vsxe.v vs3, (rs1), vs2, vm # SEW # Vector unorderedindexed store instructions vsuxb.v vs3, (rs1), vs2, vm # 8b vsuxh.v vs3, (rs1), vs2, vm # 16b vsuxw.v vs3, (rs1), vs2, vm # 32b vsuxe.v vs3, (rs1), vs2, vm # SEW
7.7. Unitstride FaultOnlyFirst Loads
The unitstride faultonlyfirst load instructions are used to vectorize
loops with datadependent exit conditions (while loops). These
instructions execute as a regular load except that they will only take
a trap on element 0. If an element > 0 raises an exception, that
element and all following elements in the destination vector
register are not modified, and the vector length vl
is reduced to the
number of elements processed without a trap.
vlbff.v vd, (rs1), vm # 8b vlhff.v vd, (rs1), vm # 16b vlwff.v vd, (rs1), vm # 32b vlbuff.v vd, (rs1), vm # unsigned 8b vlhuff.v vd, (rs1), vm # unsigned 16b vlwuff.v vd, (rs1), vm # unsigned 32b vleff.v vd, (rs1), vm # SEW
strlen example using unitstride faultonlyfirst instruction # size_t strlen(const char *str) # a0 holds *str strlen: mv a3, a0 # Save start li t0, 1 # Infinite AVL loop: vsetvli a1, t0, e8 # Vector of bytes of maximum length vlbff.v v1, (a3) # Load bytes csrr a1, vl # Get bytes read vmseq.vi v0, v1, 0 # Set v0[i] where v1[i] = 0 vfirst.m a2, v0 # Find first set bit add a3, a3, a1 # Bump pointer bltz a2, loop # Not found? add a0, a0, a1 # Sum start + bump add a3, a3, a2 # Add index sub a0, a3, a0 # Subtract start address+bump ret
Note

Strided and scatter/gather faultonlyfirst instructions are not provided as they represent a large security hole, allowing software to check multiple random pages for accessibility without experiencing a trap. The unitstride versions only allow probing a region immediately contiguous to a known region, and so do not appreciably impact security. It is possible that security mitigations can be implemented to allow faultonlyfirst variants of noncontiguous accesses in future vector extensions. 
7.8. Vector Load/Store Segment Instructions (Zvlsseg
)
Note

This set of instructions are intended to be included in the base "V" extension. 
The vector load/store segment instructions move multiple contiguous fields in memory to and from consecutively numbered vector registers.
Note

These operations support operations on "arrayofstructures" datatypes by unpacking each field in a structure into separate vector registers. 
As for regular vector loads and stores, the width encoding gives the size of the memory elements, which are homogeneous in size, while SEW encodes the size of the register elements.
The threebit nf
field in the vector instruction encoding is an
unsigned integer that contains one less than the number of fields per
segment, NFIELDS.
nf[2:0]  NFIELDS  

0 
0 
0 
1 
0 
0 
1 
2 
0 
1 
0 
3 
0 
1 
1 
4 
1 
0 
0 
5 
1 
0 
1 
6 
1 
1 
0 
7 
1 
1 
1 
8 
The LMUL setting must be such that LMUL * NFIELDS ⇐ 8, otherwise an illegal instruction exception is raised.
Note

The product LMUL * NFIELDS represents the number of underlying vector registers that will be touched by a segmented load or store instruction. This constraint makes this total no larger than 1/4 of the architectural register file, and the same as for regular operations with LMUL=8. This constraint could be weakened in a future draft. 
Each field will be held in successively numbered vector register groups. When LMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when LMUL=2 and NFIELDS=4, each field’s vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number).
Note

An earlier version imposed a vector register number constraint, but this decreased ability to make use of all registers when NFIELDS was not a power of 2. 
If the vector register numbers accessed by the segment load or store would increment past 31, then an illegal instruction exception is raised.
Note

This constraint is to help provide forwardcompatibility with a future longer instruction encoding that has more addressable vector registers. 
The vl
register gives the number of structures to move, which is
equal to the number of elements transferred to each vector register
group. Masking is also applied at the level of whole structures.
If a trap is taken, vstart
is in units of structures.
7.8.1. Vector UnitStride Segment Loads and Stores
The vector unitstride load and store segment instructions move packed contiguous segments ("arrayofstructures") into multiple destination vector register groups.
Note

For segments with heterogeneoussized fields, software can later unpack fields using additional instructions after the segment load brings the values into the separate vector registers. 
The assembler prefixes vlseg
/vsseg
are used for unitstride
segment loads and stores respectively.
# Format vlseg<nf>{b,h,w}.v vd, (rs1), vm # Unitstride signed segment load template vlseg<nf>e.v vd, (rs1), vm # Unitstride segment load template vlseg<nf>{b,h,w}u.v vd, (rs1), vm # Unitstride unsigned segment load template vsseg<nf>{b,h,w,e}.v vs3, (rs1), vm # Unitstride segment store template # Examples vlseg2b.v vd, (rs1), vm # Load vector of signed 2*1byte segments into vd, vd+1 vlseg3bu.v vd, (rs1), vm # Load vector of unsigned 3*1byte segments into vd, vd+1, vd+2 vlseg7w.v vd, (rs1), vm # Load vector of 7*4byte segments into vd, vd+1, ... vd+6 vlseg8e.v vd, (rs1), vm # Load vector of 8*SEWbyte segments into vd, vd+1, .. vd+7 vsseg3b.v vs3, (rs1), vm # Store packed vector of 3*1byte segments from vs3,vs3+1,vs3+2 to memory
For loads, the vd
register will hold the first field loaded from the
segment. For stores, the vs3
register is read to provide the first
field to be stored in each segment.
# Example 1 # Memory structure holds packed RGB pixels (24bit data structure, 8bpp) vlseg3bu.v v8, (a0), vm # v8 holds the red pixels # v9 holds the green pixels # v10 holds the blue pixels # Example 2 # Memory structure holds complex values, 32b for real and 32b for imaginary vlseg2w.v v8, (a0), vm # v8 holds real # v9 holds imaginary
There are also faultonlyfirst versions of the unitstride instructions.
# Template for vector faultonlyfirst unitstride segment loads and stores. vlseg<nf>{b,h,w}ff.v vd, (rs1), vm # Unitstride signed faultonlyfirst segment loads vlseg<nf>eff.v vd, (rs1), vm # Unitstride faultonlyfirst segment loads vlseg<nf>{b,h,w}uff.v vd, (rs1), vm # Unitstride unsigned faultonlyfirst segment loads
7.8.2. Vector Strided Segment Loads and Stores
Vector strided segment loads and stores move contiguous segments where
each segment is separated by the byte stride offset given in the rs2
GPR argument.
Note

Negative and zero strides are supported. 
# Format vlsseg<nf>{b,h,w}.v vd, (rs1), rs2, vm # Strided signed segment loads vlsseg<nf>e.v vd, (rs1), rs2, vm # Strided segment loads vlsseg<nf>{b,h,w}u.v vd, (rs1), rs2, vm # Strided unsigned segment loads vssseg<nf>{b,h,w,e}.v vs3, (rs1), rs2, vm # Strided segment stores # Examples vlsseg3b.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i], # and bytes at addresses x5+i*x6+1 into v5[i], # and bytes at addresses x5+i*x6+2 into v6[i]. # Examples vssseg2w.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6 # and words from v3[i] to address x5+i*x6+4
For strided segment stores where the byte stride is such that segments could overlap in memory, the segments must appear to be written in element order.
7.8.3. Vector Indexed Segment Loads and Stores
Vector indexed segment loads and stores move contiguous segments where
each segment is located at an address given by adding the scalar base
address in the rs1
field to byte offsets in vector register vs2
.
# Format vlxseg<nf>{b,h,w}.v vd, (rs1), vs2, vm # Indexed signed segment loads vlxseg<nf>e.v vd, (rs1), vs2, vm # Indexed segment loads vlxseg<nf>{b,h,w}u.v vd, (rs1), vs2, vm # Indexed unsigned segment loads vsxseg<nf>{b,h,w,e}.v vs3, (rs1), vs2, vm # Indexed segment stores # Examples vlxseg3bu.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i], # and bytes at addresses x5+v3[i]+1 into v5[i], # and bytes at addresses x5+v3[i]+2 into v6[i]. # Examples vsxseg2w.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i] # and words from v3[i] to address x5+v5[i]+4
For vector indexed segment loads, the destination vector register groups
cannot overlap the source vector register group (specified by vs2
), nor can
they overlap the mask register if masked, else an illegal instruction
exception is raised.
Note

This constraint supports restart of indexed segment loads that raise exceptions partway through loading a structure. 
Only ordered indexed segment stores are provided. The segments must appear to be written in element order.
7.9. Vector Load/Store Whole Register Instructions
Note

These instructions are still under early consideration for inclusion. 
These instructions load and store whole vector registers (i.e., VLEN
bits), ignoring the settings in the vl
and vtype
registers.
Note

These instructions are intended to be used to save and restore
vector registers when the type and length of the current contents of
the vector register is not known, or where modifying vl and vtype
would be costly. Examples include compiler register spills, vector
function calls where values are passed in vector registers, interrupt
handlers, and OS context switches.

Format for Vector Load Whole Register Instructions under LOADFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  000  1  01000  rs1  111  vd 0000111 VL<nf>R Format for Vector Store Whole Register Instructions under STOREFP major opcode 31 29 28 26 25 24 20 19 15 14 12 11 7 6 0 nf  000  1  01000  rs1  111  vs3 0100111 VS<nf>R
The instructions operate similarly to unmasked unitstride load and
store instructions of elements, with the base address passed in the
scalar x
register specified by rs1
.
The instructions transfer a single vector register specified by vd
for loads and vs3
for stores. The registers are transferred to and
from memory as if SEW=8 and LMUL=1.
Note

The vector whole register load instructions are encoded similar
to unmasked zeroextended unitstride loads of elements, with the nf
field encoding how many vector registers to load and store. The
vector whole register store instructions are encoded similar to
unmasked unitstride store of elements. The current base
specification only mandates nf =0 is supported, with other values of
nf reserved. In a future extension, when multiple registers are
transferred, the vector register contents are mapped to contiguous
bytes in memory as if LMUL=1, with the lowestnumbered vector register
held in the lowestnumbered memory addresses. The nf field encodes
the number of vector registers to transfer, numbered successively
after the base. The base register plus the nf value cannot exceed
31, else an illegal instruction exception is raised.

# Format vl1r.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 vs1r.v v3, (a1) # Store v3 to address in a1
8. Vector AMO Operations (Zvamo
)
Note

Profiles will dictate whether vector AMO operations are supported. The expectation is that the base "V" extension used for the Unix profile will require vector AMO operations. 
If vector AMO instructions are supported, then the scalar Zaamo instructions (atomic operations from the standard A extension) must be present.
Vector AMO operations are encoded using the unused width encodings under the standard AMO major opcode. Each active element performs an atomic readmodifywrite of a single memory location.
Format for Vector AMO Instructions under AMO major opcode 31 27 26 25 24 20 19 15 14 12 11 7 6 0 amoop wd vm  vs2  rs1  width  vs3/vd 0101111 VAMO* 5 1 1 5 5 3 5 7
vs2[4:0] specifies v register holding address vs3/vd[4:0] specifies v register holding source operand and destination vm specifies vector mask width[2:0] specifies size of memory elements, and distinguishes from scalar AMO amoop[4:0] specifies the AMO operation wd specifies whether the original memory value is written to vd (1=yes, 0=no)
AMOs have the same addressing mode as indexed operations except with
no immediate offset. A vector of byte offsets in register vs2
are
added to the scalar base register in rs1
to give the addresses of
the AMO operations.
The vs2
vector register supplies the byte offset of each element,
while the vs3
vector register supplies the source data for the
atomic memory operation.
If the wd
bit is set, the vd
register is written with the initial
value of the memory element. If the wd
bit is clear, the vd
register is not written.
Note

When wd is clear, the memory system does not need to return
the original memory value, and the original values in vd will be
preserved.

Note

The AMOs were defined to overwrite source data partly to reduce total memory pipeline read port count for implementations with register renaming. Also, to support the same addressing mode as vector indexed operations, and because vector AMOs are less likely to need results given that the primary use is parallel inmemory reductions. 
Vector AMOs operate as if aq
and rl
bits were zero on each element
with regard to ordering relative to other instructions in the same
hart.
Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction.
Width [2:0]  Mem bits  Reg bits  Opcode  

Standard scalar AMO 
0 
1 
0 
32 
XLEN 
AMO*.W 
Standard scalar AMO 
0 
1 
1 
64 
XLEN 
AMO*.D 
Standard scalar AMO 
1 
0 
0 
128 
XLEN 
AMO*.Q 
Vector AMO 
1 
1 
0 
32 
vl*SEW 
VAMO*W.V 
Vector AMO 
1 
1 
1 
SEW 
vl*SEW 
VAMO*E.V 
Mem bits is the size of element accessed in memory
Reg bits is the size of element accessed in register
There are two widths of vector AMO, one for 32bit words and one for SEWbit words. For the 32bit vector AMO operations, SEW must be at least 32 bits, otherwise an illegal instruction exception is raised. If SEW > 32 bits, the value returned from memory is signextended to fill SEW.
If SEW is less than XLEN, then addresses in the vector vs2
are
zeroextended to XLEN. If SEW is greater than XLEN, an illegal
instruction exception is raised.
Note

Signextending addresses held in narrower SEW might match expectations on how narrow virtual addresses are usually handled, but requires slightly different hardware than for the zeroextension of offsets used in indexed load/stores. By far the most common use case for vector AMO instructions is expected to be for address elements that have SEW=XLEN, where there is no extension, so the decision was made to simplify the hardware. Software can always explicitly promote narrower addresses to signextended wider addresses if this is needed. 
Vector AMO instructions are only supported for the memory element widths supported by AMOs in the implementation’s scalar architecture. Other widths raise an illegal instruction exception.
The vector amoop[4:0]
field uses the same encoding as the scalar
5bit AMO instruction field, except that LR and SC are not supported.
amoop  opcode  

0 
0 
0 
0 
1 
vamoswap 
0 
0 
0 
0 
0 
vamoadd 
0 
0 
1 
0 
0 
vamoxor 
0 
1 
1 
0 
0 
vamoand 
0 
1 
0 
0 
0 
vamoor 
1 
0 
0 
0 
0 
vamomin 
1 
0 
1 
0 
0 
vamomax 
1 
1 
0 
0 
0 
vamominu 
1 
1 
1 
0 
0 
vamomaxu 
The assembly syntax uses x0
in the destination register position to
indicate the return value is not required (wd=0
).
# 32bit vector AMOs vamoswapw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoswapw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoaddw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoaddw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoxorw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoxorw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoandw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoandw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoorw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoorw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamominw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamominw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamomaxw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamominuw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamominuw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxuw.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamomaxuw.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 # SEWbit vector AMOs vamoswape.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoswape.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoadde.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoadde.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoxore.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoxore.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoande.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoande.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamoore.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamoore.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamomine.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamomine.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxe.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamomaxe.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamominue.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamominue.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0 vamomaxue.v vd, (rs1), v2, vd, v0.t # Write original value to register, wd=1 vamomaxue.v x0, (rs1), v2, vs3, v0.t # Do not write original value to register, wd=0
9. Vector Memory Alignment Constraints
If the elements accessed by a vector memory instruction are not naturally aligned to the memory element size, either an address misaligned exception is raised on that element or the element is transferred successfully.
Vector memory accesses follow the same rules for atomicity as scalar memory accesses.
10. Vector Memory Consistency Model
Vector memory instructions appear to execute in program order on the local hart. Vector memory instructions follow RVWMO at the instruction level, and element operations are ordered within the instruction as if performed by an elementordered sequence of syntactically independent scalar instructions. Vector indexedordered stores write elements to memory in element order. Vector indexedunordered stores do not preserve element order for writes within a single vector store instruction.
Note

Need to flesh out details. 
11. Vector Arithmetic Instruction Formats
The vector arithmetic instructions use a new major opcode (OPV =
1010111_{2}) which neighbors OPFP. The threebit funct3
field is
used to define subcategories of vector instructions.
Formats for Vector Arithmetic Instructions under OPV major opcode 31 26 25 24 20 19 15 14 12 11 7 6 0 funct6  vm  vs2  vs1  0 0 0  vd 1010111 OPV (OPIVV) funct6  vm  vs2  vs1  0 0 1  vd/rd 1010111 OPV (OPFVV) funct6  vm  vs2  vs1  0 1 0  vd/rd 1010111 OPV (OPMVV) funct6  vm  vs2  simm5  0 1 1  vd 1010111 OPV (OPIVI) funct6  vm  vs2  rs1  1 0 0  vd 1010111 OPV (OPIVX) funct6  vm  vs2  rs1  1 0 1  vd 1010111 OPV (OPFVF) funct6  vm  vs2  rs1  1 1 0  vd/rd 1010111 OPV (OPMVX) 6 1 5 5 3 5 7
11.1. Vector Arithmetic Instruction encoding
The funct3
field encodes the operand type and source locations.
funct3[2:0]  Operands  Source of scalar(s)  

0 
0 
0 
OPIVV 
vectorvector 
 
0 
0 
1 
OPFVV 
vectorvector 
 
0 
1 
0 
OPMVV 
vectorvector 
 
0 
1 
1 
OPIVI 
vectorimmediate 
imm[4:0] 
1 
0 
0 
OPIVX 
vectorscalar 
GPR x register rs1 
1 
0 
1 
OPFVF 
vectorscalar 
FP f register rs1 
1 
1 
0 
OPMVX 
vectorscalar 
GPR x register rs1 
1 
1 
1 
OPCFG 
scalarsimms 
GPR x register rs1 & rs2/imm 
Integer operations are performed using unsigned or two’scomplement signed integer arithmetic depending on the opcode.
All standard vector floatingpoint arithmetic operations follow the
IEEE754/2008 standard. All vector floatingpoint operations use the
dynamic rounding mode in the frm
register.
Vectorvector operations take two vectors of operands from vector
register groups specified by vs2
and vs1
respectively.
Vectorscalar operations can have three possible forms, but in all
cases take one vector of operands from a vector register group
specified by vs2
and a second scalar source operand from one of
three alternative sources.

For integer operations, the scalar can be a 5bit immediate encoded in the
rs1
field. The value is sign or zeroextended to SEW bits. 
For integer operations, the scalar can be taken from the scalar
x
register specified byrs1
. If XLEN>SEW, the leastsignificant SEW bits of thex
register are used. If XLEN<SEW, the value from thex
register is signextended to SEW bits. 
For floatingpoint operations, the scalar can be taken from a scalar
f
register. If FLEN>SEW, the value in thef
registers is checked for a valid NaNboxed value, in which case the leastsignificant SEW bits of the `f`register are used, else the canonical NaN value is used. If FLEN<SEW, the value is NaNboxed (oneextended) to SEW.
Note

The proposed Zfinx variants will take the floatingpoint scalar
argument from the x registers.

Vector arithmetic instructions are masked under control of the vm
field.
# Assembly syntax pattern for vector binary arithmetic instructions # Operations returning vector results, masked by vm (v0.t, <nothing>) vop.vv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vop.vx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1] vop.vi vd, vs2, imm, vm # integer vectorimmediate vd[i] = vs2[i] op imm vfop.vv vd, vs2, vs1, vm # FP vectorvector operation vd[i] = vs2[i] fop vs1[i] vfop.vf vd, vs2, rs1, vm # FP vectorscalar operation vd[i] = vs2[i] fop f[rs1]
Note

In the encoding, vs2 is the first operand, while rs1/simm5
is the second operand. This is the opposite to the standard scalar
ordering. This arrangement retains the existing encoding conventions
that instructions that read only one scalar register, read it from
rs1 , and that 5bit immediates are sourced from the rs1 field.

# Assembly syntax pattern for vector ternary arithmetic instructions (multiplyadd) # Integer operations overwriting sum input vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vs2[i] + vd[i] # Integer operations overwriting product input vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vd[i] + vs2[i] # Floatingpoint operations overwriting sum input vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vs2[i] + vd[i] # Floatingpoint operations overwriting product input vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vd[i] + vs2[i]
Note

For ternary multiplyadd operations, the assembler syntax always
places the destination vector register first, followed by either rs1
or vs1 , then vs2 . This ordering provides a more natural reading
of the assembler for these ternary operations, as the multiply
operands are always next to each other.

11.2. Widening Vector Arithmetic Instructions
A few vector arithmetic instructions are defined to be widening operations where the destination elements are 2*SEW wide and are stored in a vector register group with twice the number of vector registers.
The first operand can be either single or doublewidth. These are
generally written with a vw*
prefix on the opcode or vfw*
for
vector floatingpoint operations.
Assembly syntax pattern for vector widening arithmetic instructions # Doublewidth result, two singlewidth sources: 2*SEW = SEW op SEW vwop.vv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vwop.vx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1] # Doublewidth result, first source doublewidth, second source singlewidth: 2*SEW = 2*SEW op SEW vwop.wv vd, vs2, vs1, vm # integer vectorvector vd[i] = vs2[i] op vs1[i] vwop.wx vd, vs2, rs1, vm # integer vectorscalar vd[i] = vs2[i] op x[rs1]
Note

Originally, a w suffix was used on opcode, but this could be
confused with the use of a w suffix to mean wordsized operations in
doubleword integers, so the w was moved to prefix.

Note

The floatingpoint widening operations were changed to vfw*
from vwf* to be more consistent with any scalar widening
floatingpoint operations that will be written as fw* .

Note

For integer multiplyadd, another possible widening option
increases the size of the accumulator to 4*SEW (i.e., 4*SEW +=
SEW*SEW). These would be distinguished by a vw4* prefix on the
opcode. These are not included at this time, but are a possible
addition to spec.

The destination vector register group results are arranged as if both SEW and LMUL were at twice their current settings (i.e., the destination element width is 2*SEW, and the destination vector register group LMUL is 2*LMUL).
For all widening instructions, the destination element width must be a supported element width and the destination LMUL value must also be a supported LMUL value (≤8, i.e., current LMUL must be ≤4), otherwise an illegal instruction exception is raised.
The destination vector register group must be specified using a vector register number that is valid for the destination’s LMUL value, otherwise an illegal instruction exception is raised.
The destination vector register group cannot overlap a source vector register group of a different element width (including the mask register if masked), otherwise an illegal instruction exception is raised.
Note

This constraint is necessary to support restart with nonzero
vstart .

Note

For the vw<op>.wv vd, vs2, vs1 format instructions, it is legal
for vd to equal vs2.

11.3. Narrowing Vector Arithmetic Instructions
A few instructions are provided to convert doublewidth source vectors into singlewidth destination vectors. These instructions convert a vector register group organized as if LMUL and SEW were twice the current settings, and convert to a vector register group with the current LMUL/SEW vectors/elements.
If (2*LMUL > 8), or (2 * SEW) > ELEN, an illegal instruction exception is raised.
Note

An alternative design decision would have been to treat LMUL as defining the size of the source vector register group. The choice here is motivated by the belief the chosen approach will require fewer LMUL changes. 
The source and destination vector register groups have to be specified with a vector register number that is legal for the source and destination LMUL value respectively, otherwise an illegal instruction exception is raised.
Where there is a second source vector register group (specified by
vs1
), this has the same (narrower) width as the result.
The destination vector register group cannot overlap the first source
vector register group (specified by vs2
). The destination vector
register group cannot overlap the mask register if used, unless
LMUL=1. If either constraint is violated, an illegal instruction
exception is raised.
Note

It is safe to overwrite a second source vector register group with the same LMUL and element width as the result, or to overwrite a mask register when LMUL=1. 
A vn*
prefix on the opcode is used to distinguish these instructions
in the assembler, or a vfn*
prefix for narrowing floatingpoint
opcodes. The doublewidth source vector register group is signified
by a w
in the source operand suffix (e.g., vnsra.wv
)
Note

Comparison operations that set a mask register are also implicitly a narrowing operation. 
12. Vector Integer Arithmetic Instructions
A set of vector integer arithmetic instructions are provided.
12.1. Vector SingleWidth Integer Add and Subtract
Vector integer add and subtract are provided. Reversesubtract instructions are also provided for the vectorscalar forms.
# Integer adds. vadd.vv vd, vs2, vs1, vm # Vectorvector vadd.vx vd, vs2, rs1, vm # vectorscalar vadd.vi vd, vs2, imm, vm # vectorimmediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vectorvector vsub.vx vd, vs2, rs1, vm # vectorscalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1  vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm  vs2[i]
12.2. Vector Widening Integer Add/Subtract
The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign or zeroextended before forming the doublewidth sum.
# Widening unsigned integer add/subtract, 2*SEW = SEW +/ SEW vwaddu.vv vd, vs2, vs1, vm # vectorvector vwaddu.vx vd, vs2, rs1, vm # vectorscalar vwsubu.vv vd, vs2, vs1, vm # vectorvector vwsubu.vx vd, vs2, rs1, vm # vectorscalar # Widening signed integer add/subtract, 2*SEW = SEW +/ SEW vwadd.vv vd, vs2, vs1, vm # vectorvector vwadd.vx vd, vs2, rs1, vm # vectorscalar vwsub.vv vd, vs2, vs1, vm # vectorvector vwsub.vx vd, vs2, rs1, vm # vectorscalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/ SEW vwaddu.wv vd, vs2, vs1, vm # vectorvector vwaddu.wx vd, vs2, rs1, vm # vectorscalar vwsubu.wv vd, vs2, vs1, vm # vectorvector vwsubu.wx vd, vs2, rs1, vm # vectorscalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/ SEW vwadd.wv vd, vs2, vs1, vm # vectorvector vwadd.wx vd, vs2, rs1, vm # vectorscalar vwsub.wv vd, vs2, vs1, vm # vectorvector vwsub.wx vd, vs2, rs1, vm # vectorscalar
Note

An integer value can be doubled in width using the widening add
instructions with a scalar operand of x0 . Can define assembly
pseudoinstructions vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm and
vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm .

12.3. Vector Integer AddwithCarry / SubtractwithBorrow Instructions
To support multiword integer arithmetic, instructions that operate on a carry bit are provided. For each operation (add or subtract), two instructions are provided: one to provide the result (SEW width), and the second to generate the carry output (single bit encoded as a mask boolean).
The carry inputs and outputs are represented using the mask register
layout as described in Section Mask Register Layout. Due to
encoding constraints, the carry input must come from the implicit v0
register, but carry outputs can be written to any vector register that
respects the source/destination overlap restrictions below.
vadc
and vsbc
add or subtract the source operands and the carryin or
borrowin, and write the result to vector register vd
.
These instructions are encoded as masked instructions (vm=0
), but they operate
on and write back all body elements.
Encodings corresponding to the unmasked versions (vm=1
) are reserved.
vmadc
and vmsbc
add or subtract the source operands, optionally add the
carryin or subtract the borrowin if masked (vm=0
), and write the result back
to mask register vd
.
If unmasked (vm=1
), there is no carryin or borrowin.
These instructions operate on and write back all body elements, even if
masked.
# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0[i].LSB vadc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = vs2[i] + x[rs1] + v0[i].LSB vadc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = vs2[i] + imm + v0[i].LSB vadc.vim vd, vs2, imm, v0 # Vectorimmediate # Produce carry out in mask register format # vd[i] = carry_out(vs2[i] + vs1[i] + v0[i].LSB) vmadc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = carry_out(vs2[i] + x[rs1] + v0[i].LSB) vmadc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = carry_out(vs2[i] + imm + v0[i].LSB) vmadc.vim vd, vs2, imm, v0 # Vectorimmediate # vd[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vectorvector, no carryin # vd[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vectorscalar, no carryin # vd[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vectorimmediate, no carryin
Because implementing a carry propagation requires executing two instructions with unchanged inputs, destructive accumulations will require an additional move to obtain correct results.
# Example multiword arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 # Calc new sum vmcpy.m v0, v1 # Move temp carry into v0 for next word
The subtract with borrow instruction vsbc
performs the equivalent
function to support long word arithmetic for subtraction. There are
no subtract with immediate instructions.
# Produce difference with borrow. # vd[i] = vs2[i]  vs1[i]  v0[i].LSB vsbc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = vs2[i]  x[rs1]  v0[i].LSB vsbc.vxm vd, vs2, rs1, v0 # Vectorscalar # Produce borrow out in mask register format # vd[i] = borrow_out(vs2[i]  vs1[i]  v0[i].LSB) vmsbc.vvm vd, vs2, vs1, v0 # Vectorvector # vd[i] = borrow_out(vs2[i]  x[rs1]  v0[i].LSB) vmsbc.vxm vd, vs2, rs1, v0 # Vectorscalar # vd[i] = borrow_out(vs2[i]  vs1[i]) vmsbc.vv vd, vs2, vs1 # Vectorvector, no borrowin # vd[i] = borrow_out(vs2[i]  x[rs1]) vmsbc.vx vd, vs2, rs1 # Vectorscalar, no borrowin
For vmsbc
, the borrow is defined to be 1 iff the difference, prior to
truncation, is negative.
For vadc
and vsbc
, an illegal instruction exception is raised
if the destination vector register is v0
and LMUL > 1.
Note

This constraint corresponds to the constraint on masked vector operations that overwrite the mask register. 
For vmadc
and vmsbc
, an illegal instruction exception is raised if
the destination vector register overlaps a source vector register
group and LMUL > 1.
12.4. Vector Bitwise Logical Instructions
# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vectorvector vand.vx vd, vs2, rs1, vm # vectorscalar vand.vi vd, vs2, imm, vm # vectorimmediate vor.vv vd, vs2, vs1, vm # Vectorvector vor.vx vd, vs2, rs1, vm # vectorscalar vor.vi vd, vs2, imm, vm # vectorimmediate vxor.vv vd, vs2, vs1, vm # Vectorvector vxor.vx vd, vs2, rs1, vm # vectorscalar vxor.vi vd, vs2, imm, vm # vectorimmediate
Note

With an immediate of 1, scalarimmediate forms of the vxor
instruction provide a bitwise NOT operation. This can be provided as
an assembler pseudoinstruction vnot.v .

12.5. Vector SingleWidth Bit Shift Instructions
A full complement of vector shift instructions are provided, including logical shift left, and logical (zeroextending) and arithmetic (signextending) shift right.
# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vectorvector vsll.vx vd, vs2, rs1, vm # vectorscalar vsll.vi vd, vs2, uimm, vm # vectorimmediate vsrl.vv vd, vs2, vs1, vm # Vectorvector vsrl.vx vd, vs2, rs1, vm # vectorscalar vsrl.vi vd, vs2, uimm, vm # vectorimmediate vsra.vv vd, vs2, vs1, vm # Vectorvector vsra.vx vd, vs2, rs1, vm # vectorscalar vsra.vi vd, vs2, uimm, vm # vectorimmediate
Only the low lg2(SEW) bits are read to obtain the shift amount from a register value.
The immediate is treated as an unsigned shift amount, with a maximum shift amount of 31.
12.6. Vector Narrowing Integer Right Shift Instructions
The narrowing right shifts extract a smaller field from a wider
operand and have both zeroextending (srl
) and signextending
(sra
) forms. The shift amount can come from a vector or a scalar
x
register or a 5bit immediate. The low lg2(2*SEW) bits of the
vector or scalar shift amount value are used (e.g., the low 6 bits for
a SEW=64bit to SEW=32bit narrowing operation). The unsigned immediate form
supports shift amounts up to 31 only.
# Narrowing shift right logical, SEW = (2*SEW) >> SEW vnsrl.wv vd, vs2, vs1, vm # vectorvector vnsrl.wx vd, vs2, rs1, vm # vectorscalar vnsrl.wi vd, vs2, uimm, vm # vectorimmediate # Narrowing shift right arithmetic, SEW = (2*SEW) >> SEW vnsra.wv vd, vs2, vs1, vm # vectorvector vnsra.wx vd, vs2, rs1, vm # vectorscalar vnsra.wi vd, vs2, uimm, vm # vectorimmediate
Note

It could be useful to add support for n4 variants, where the
destination is 1/4 width of source.

12.7. Vector Integer Comparison Instructions
The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in Section Mask Register Layout.
# Set if equal vmseq.vv vd, vs2, vs1, vm # Vectorvector vmseq.vx vd, vs2, rs1, vm # vectorscalar vmseq.vi vd, vs2, imm, vm # vectorimmediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vectorvector vmsne.vx vd, vs2, rs1, vm # vectorscalar vmsne.vi vd, vs2, imm, vm # vectorimmediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vectorvector vmsltu.vx vd, vs2, rs1, vm # Vectorscalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vectorvector vmslt.vx vd, vs2, rs1, vm # vectorscalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vectorvector vmsleu.vx vd, vs2, rs1, vm # vectorscalar vmsleu.vi vd, vs2, imm, vm # Vectorimmediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vectorvector vmsle.vx vd, vs2, rs1, vm # vectorscalar vmsle.vi vd, vs2, imm, vm # vectorimmediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vectorscalar vmsgtu.vi vd, vs2, imm, vm # Vectorimmediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vectorscalar vmsgt.vi vd, vs2, imm, vm # Vectorimmediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vectorscalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vectorscalar
The following table indicates how all comparisons are implemented in native machine code.
Comparison Assembler Mapping Assembler Pseudoinstruction va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below va < i vmsle{u}.vi vd, va, i1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i1, vm vmsge{u}.vi vd, va, i, vm va, vb vector register groups x scalar integer register i immediate
Note

The immediate forms of vmslt{u}.vi are not provided as the
immediate value can be decreased by 1 and the vmsle{u}.vi variants
used instead. The vmsle.vi range is 16 to 15, resulting in an
effective vmslt.vi range of 15 to 16. The vmsleu.vi range is 0 to
15 (and (~0)15 to ~0 ), giving an effective vmsltu.vi range of 1 to 16
(Note, vmsltu.vi with immediate 0 is not useful as it is always
false). Similarly, vmsge{u}.vi is not provided and the comparison is
implemented using vmsgt{u}.vi with the immediate decremented by one.
The resulting effective vmsge.vi range is 15 to 16, and the
resulting effective vmsgeu.vi range is 1 to 16 (Note, vmsgeu.vi with
immediate 0 is not useful as it is always true).

Note

The vmsgt forms for register scalar and immediates are provided
to allow a single comparison instruction to provide the correct
polarity of mask value without using additional mask logical
instructions.

To reduce encoding space, the vmsge{u}.vx
form is not directly
provided, and so the va ≥ x
case requires special treatment.
Note

The vmsge{u}.vx could potentially be encoded in a
nonorthogonal way under the unused OPIVI variant of vmslt{u} . These
would be the only instructions in OPIVI that use a scalar `x`register
however. Alternatively, a further two funct6 encodings could be used,
but these would have a different operand format (writes to mask
register) than others in the same group of 8 funct6 encodings. The
current PoR is to omit these instructions and to synthesize where
needed as described below.

The vmsge{u}.vx
operation can be synthesized by reducing the
value of x
by 1 and using the vmsgt{u}.vx
instruction, when it is
known that this will not underflow the representation in x
.
Sequences to synthesize `vmsge{u}.vx` instruction va >= x, x > minimum addi t0, x, 1; vmsgt{u}.vx vd, va, t0, vm
The above sequence will usually be the most efficient implementation,
but assembler pseudoinstructions can be provided for cases where the
range of x
is unknown.
unmasked va >= x pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd masked va >= x, vd != v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 masked va >= x, any vd pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction
Comparisons effectively AND in the mask, e.g,
# (a < b) && (b < c) in two instructions vmslt.vv v0, va, vb # All body elements written vmslt.vv v0, vb, vc, v0.t # Only update at set mask
For all comparison instructions, an illegal instruction exception is raised if the destination vector register overlaps a source vector register group and LMUL > 1.
12.8. Vector Integer Min/Max Instructions
Signed and unsigned integer minimum and maximum instructions are supported.
# Unsigned minimum vminu.vv vd, vs2, vs1, vm # Vectorvector vminu.vx vd, vs2, rs1, vm # vectorscalar # Signed minimum vmin.vv vd, vs2, vs1, vm # Vectorvector vmin.vx vd, vs2, rs1, vm # vectorscalar # Unsigned maximum vmaxu.vv vd, vs2, vs1, vm # Vectorvector vmaxu.vx vd, vs2, rs1, vm # vectorscalar # Signed maximum vmax.vv vd, vs2, vs1, vm # Vectorvector vmax.vx vd, vs2, rs1, vm # vectorscalar
12.9. Vector SingleWidth Integer Multiply Instructions
The singlewidth multiply instructions perform a SEWbit*SEWbit
multiply and return an SEWbitwide result. The mulh
versions
write the high word of the product to the destination register.
# Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm # Vectorvector vmul.vx vd, vs2, rs1, vm # vectorscalar # Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm # Vectorvector vmulh.vx vd, vs2, rs1, vm # vectorscalar # Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm # Vectorvector vmulhu.vx vd, vs2, rs1, vm # vectorscalar # Signed(vs2)Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm # Vectorvector vmulhsu.vx vd, vs2, rs1, vm # vectorscalar
Note

There is no vmulhus opcode to return high half of
unsignedvector * signedscalar product.

Note

The current vmulh* opcodes perform simple fractional
multiplies, but with no option to scale, round, and/or saturate the
result. Can consider changing definition of vmulh , vmulhu ,
vmulhsu to use vxrm rounding mode when discarding low half of
product. There is no possibility of overflow in this case.

12.10. Vector Integer Divide Instructions
The divide and remainder instructions are equivalent to the RISCV standard scalar integer multiply/divides, with the same results for extreme inputs.
# Unsigned divide. vdivu.vv vd, vs2, vs1, vm # Vectorvector vdivu.vx vd, vs2, rs1, vm # vectorscalar # Signed divide vdiv.vv vd, vs2, vs1, vm # Vectorvector vdiv.vx vd, vs2, rs1, vm # vectorscalar # Unsigned remainder vremu.vv vd, vs2, vs1, vm # Vectorvector vremu.vx vd, vs2, rs1, vm # vectorscalar # Signed remainder vrem.vv vd, vs2, vs1, vm # Vectorvector vrem.vx vd, vs2, rs1, vm # vectorscalar
Note

The decision to include integer divide and remainder was contentious. The argument in favor is that without a standard instruction, software would have to pick some algorithm to perform the operation, which would likely perform poorly on some microarchitectures versus others. 
Note

There is no instruction to perform a "scalar divide by vector" operation. 
12.11. Vector Widening Integer Multiply Instructions
The widening integer multiply instructions return the full 2*SEWbit product from an SEWbit*SEWbit multiply.
# Widening signedinteger multiply vwmul.vv vd, vs2, vs1, vm# vectorvector vwmul.vx vd, vs2, rs1, vm # vectorscalar # Widening unsignedinteger multiply vwmulu.vv vd, vs2, vs1, vm # vectorvector vwmulu.vx vd, vs2, rs1, vm # vectorscalar # Widening signedunsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm # vectorvector vwmulsu.vx vd, vs2, rs1, vm # vectorscalar
12.12. Vector SingleWidth Integer MultiplyAdd Instructions
The integer multiplyadd instructions are destructive and are provided
in two forms, one that overwrites the addend or minuend
(vmacc
, vnmsac
) and one that overwrites the first multiplicand
(vmadd
, vnmsub
).
The low half of the product is added or subtracted from the third operand.
Note

"sac" is intended to be read as "subtract from accumulator". The
opcode is "vnmsac" to match the (unfortunately counterintuitive)
floatingpoint fnmsub instruction definition. Similarly for the
"vnmsub" opcode.

# Integer multiplyadd, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Integer multiplysub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vs2[i]) + vd[i] # Integer multiplyadd, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] # Integer multiplysub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i]
12.13. Vector Widening Integer MultiplyAdd Instructions
The widening integer multiplyadd instructions add a SEWbit*SEWbit multiply result to (from) a 2*SEWbit value and produce a 2*SEWbit result. All combinations of signed and unsigned multiply operands are supported.
# Widening unsignedinteger multiplyadd, overwrite addend vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signedinteger multiplyadd, overwrite addend vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signedunsignedinteger multiplyadd, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Widening unsignedsignedinteger multiplyadd, overwrite addend vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
12.14. Vector QuadWidening Integer MultiplyAdd Instructions (Extension Zvqmac
)
The quadwidening integer multiplyadd instructions add a SEWbit*SEWbit multiply result to (from) a 4*SEWbit value and produce a 4*SEWbit result. All combinations of signed and unsigned multiply operands are supported.
Note

These instructions are currently not planned to be part of the base V extension. 
Note

On ELEN=32 machines, only 8b * 8b = 16b products accumulated in a 32b accumulator would be supported. Machines with ELEN=64 would also add 16b * 16b = 32b products accumulated in 64b. 
# Quadwidening unsignedinteger multiplyadd, overwrite addend vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Quadwidening signedinteger multiplyadd, overwrite addend vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Quadwidening signedunsignedinteger multiplyadd, overwrite addend vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Quadwidening unsignedsignedinteger multiplyadd, overwrite addend vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
12.15. Vector Integer Merge Instructions
The vector integer merge instructions combine two source operands
based on the mask field. Unlike regular arithmetic instructions, the
merge operates on all body elements (i.e., the set of elements from
vstart
up to the current vector length in vl
).
The vmerge
instructions are always masked (vm=0
).
The instructions combine two
sources as follows. At elements where the mask value is zero, the
first operand is copied to the destination element, otherwise the
second operand is copied to the destination element. The first
operand is always a vector register group specified by vs2
. The
second operand is a vector register group specified by vs1
or a
scalar x
register specified by rs1
or a 5bit signextended
immediate.
vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0[i].LSB ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0[i].LSB ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0[i].LSB ? imm : vs2[i]
12.16. Vector Integer Move Instructions
The vector integer move instructions copy a source operand to a vector
register group. These instructions are always unmasked (vm=1
).
The first operand specifier (vs2
) must contain v0
, and any other
vector register number in vs2
is reserved. This instruction
copies the vs1
, rs1
, or immediate operand to the first vl
locations of the destination vector register group.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = rs1 vmv.v.i vd, imm # vd[i] = imm
Note

Mask values can be widened into SEWwidth elements using a
sequence vmv.v.i vd, 0; vmerge.vim vd, vd, 1, v0 .

Note

The vector integer move instructions share the encoding with the vector
merge instructions, but with vm=1 and vs2=v0 .

13. Vector FixedPoint Arithmetic Instructions
A set of vector arithmetic instructions are provided to support fixedpoint arithmetic.
An Nbit element can hold two’scomplement signed integers in the range 2^{N1}…+2^{N1}1, and unsigned integers in the range 0 … +2^{N}1. The fixedpoint instructions help preserve precision in narrow operands by supporting scaling and rounding, and can handle overflow by saturating results into the destination format range.
Note

The widening integer operations described above can also be used to remove the possibility of overflow. 
13.1. Vector SingleWidth Saturating Add and Subtract
Saturating forms of integer add and subtract are provided, for both
signed and unsigned integers. If the result would overflow the
destination, the result is replaced with the closest representable
value, and the vxsat
bit is set.
# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vectorvector vsaddu.vx vd, vs2, rs1, vm # vectorscalar vsaddu.vi vd, vs2, imm, vm # vectorimmediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vectorvector vsadd.vx vd, vs2, rs1, vm # vectorscalar vsadd.vi vd, vs2, imm, vm # vectorimmediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vectorvector vssubu.vx vd, vs2, rs1, vm # vectorscalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vectorvector vssub.vx vd, vs2, rs1, vm # vectorscalar
13.2. Vector SingleWidth Averaging Add and Subtract
The averaging add and subtract instructions right shift the result by
one bit and round off the result according to the setting in vxrm
.
Both unsigned and signed versions are provided.
For vaaddu
, vaadd
, and vasub
, there can be no overflow in the result.
For vasubu
, overflow is ignored.
# Averaging add # Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) # Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) # Averaging subtract # Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i]  vs1[i], 1) vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i]  x[rs1], 1) # Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i]  vs1[i], 1) vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i]  x[rs1], 1)
13.3. Vector SingleWidth Fractional Multiply with Rounding and Saturation
The signed fractional multiply instruction produces a 2*SEW product of
the two SEW inputs, then shifts the result right by SEW1 bits,
rounding these bits according to vxrm
, then saturates the result to
fit into SEW bits. If the result causes saturation, the vxsat
bit
is set.
# Signed saturating and rounding fractional multiply # See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW1)) vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW1))
Note

When multiplying two Nbit signed numbers, the largest magnitude is obtained for 2^{N1} * 2^{N1} producing a result +2^{2N2}, which has a single (zero) sign bit when held in 2N bits. All other products have two sign bits in 2N bits. To retain greater precision in N result bits, the product is shifted right by one bit less than N, saturating the largest magnitude result but increasing result precision by one bit for all other products. 
13.4. Vector SingleWidth Scaling Shift Instructions
These instructions shift the input value right, and round off the
shifted out bits according to vxrm
. The scaling right shifts have
both zeroextending (vssrl
) and signextending (vssra
) forms. The
low lg2(SEW) bits of the vector or scalar shift amount value are used.
The immediate form supports shift amounts up to 31 only.
# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)
13.5. Vector Narrowing FixedPoint Clip Instructions
The vnclip
instructions are used to pack a fixedpoint value into a
narrower destination. The instructions support rounding, scaling, and
saturation into the final destination format.
The second argument (vector element, scalar value, immediate value) gives the amount to right shift the source as in the narrowing shift instructions, which provides the scaling. The low lg2(2*SEW) bits of the vector or scalar shift amount value are used (e.g., the low 6 bits for a SEW=64bit to SEW=32bit narrowing operation). The immediate form supports shift amounts up to 31 only.
# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5))
For vnclipu
/vnclip
, the rounding mode is specified in the vxrm
CSR. Rounding occurs around the leastsignificant bit of the
destination and before saturation.
For vnclipu
, the shifted rounded source value is treated as an
unsigned integer and saturates if the result would overflow the
destination viewed as an unsigned integer.
For vnclip
, the shifted rounded source value is treated as a signed
integer and saturates if the result would overflow the destination viewed
as a signed integer.
If any destination element is saturated, the vxsat
bit is set in the
vxsat
register.
14. Vector FloatingPoint Instructions
The standard vector floatingpoint instructions treat 16bit, 32bit, 64bit, and 128bit elements as IEEE754/2008compatible values. If the current SEW does not correspond to a supported IEEE floatingpoint type, an illegal instruction exception is raised.
Note

The floatingpoint element widths that are supported depend on the platform. 
Note

Platforms supporting 16bit halfprecision floatingpoint values
will also have to implement scalar halfprecision floatingpoint
support in the f registers.

The vector floatingpoint instructions have the same behavior as the scalar floatingpoint instructions with regard to NaNs.
Scalar values for vectorscalar operations can be sourced from the
standard scalar f
registers.
Note

Scalar floatingpoint values will be sourced from the integer
x registers in the proposed Zfinx variant.

14.1. Vector FloatingPoint Exception Flags
A vector floatingpoint exception at any active floatingpoint element
sets the standard FP exception flags in the fflags
register. Inactive
elements do not set FP exception flags.
14.2. Vector SingleWidth FloatingPoint Add/Subtract Instructions
# Floatingpoint add vfadd.vv vd, vs2, vs1, vm # Vectorvector vfadd.vf vd, vs2, rs1, vm # vectorscalar # Floatingpoint subtract vfsub.vv vd, vs2, vs1, vm # Vectorvector vfsub.vf vd, vs2, rs1, vm # Vectorscalar vd[i] = vs2[i]  f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalarvector vd[i] = f[rs1]  vs2[i]
14.3. Vector Widening FloatingPoint Add/Subtract Instructions
# Widening FP add/subtract, 2*SEW = SEW +/ SEW vfwadd.vv vd, vs2, vs1, vm # vectorvector vfwadd.vf vd, vs2, rs1, vm # vectorscalar vfwsub.vv vd, vs2, vs1, vm # vectorvector vfwsub.vf vd, vs2, rs1, vm # vectorscalar # Widening FP add/subtract, 2*SEW = 2*SEW +/ SEW vfwadd.wv vd, vs2, vs1, vm # vectorvector vfwadd.wf vd, vs2, rs1, vm # vectorscalar vfwsub.wv vd, vs2, vs1, vm # vectorvector vfwsub.wf vd, vs2, rs1, vm # vectorscalar
14.4. Vector SingleWidth FloatingPoint Multiply/Divide Instructions
# Floatingpoint multiply vfmul.vv vd, vs2, vs1, vm # Vectorvector vfmul.vf vd, vs2, rs1, vm # vectorscalar # Floatingpoint divide vfdiv.vv vd, vs2, vs1, vm # Vectorvector vfdiv.vf vd, vs2, rs1, vm # vectorscalar # Reverse floatingpoint divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalarvector, vd[i] = f[rs1]/vs2[i]
14.5. Vector Widening FloatingPoint Multiply
# Widening floatingpoint multiply vfwmul.vv vd, vs2, vs1, vm # vectorvector vfwmul.vf vd, vs2, rs1, vm # vectorscalar
14.6. Vector SingleWidth FloatingPoint Fused MultiplyAdd Instructions
All four varieties of fused multiplyadd are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand.
# FP multiplyaccumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP negate(multiplyaccumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i])  vd[i] vfnmacc.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i])  vd[i] # FP multiplysubtractaccumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i])  vd[i] vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i])  vd[i] # FP negate(multiplysubtractaccumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i]) + vd[i] # FP multiplyadd, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] # FP negate(multiplyadd), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i])  vs2[i] vfnmadd.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vd[i])  vs2[i] # FP multiplysub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i])  vs2[i] vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i])  vs2[i] # FP negate(multiplysub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vd[i]) + vs2[i]
Note

It would be possible to use the two unused rounding modes in the scalar FP FMA encoding to provide a few nondestructive FMAs. However, this would be the only maskable operation with three inputs and separate output. 
14.7. Vector Widening FloatingPoint Fused MultiplyAdd Instructions
The widening floatingpoint fused multiplyadd instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide.
# FP widening multiplyaccumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP widening negate(multiplyaccumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i])  vd[i] vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i])  vd[i] # FP widening multiplysubtractaccumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i])  vd[i] vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i])  vd[i] # FP widening negate(multiplysubtractaccumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = (f[rs1] * vs2[i]) + vd[i]
14.8. Vector FloatingPoint SquareRoot Instruction
This is a unary vectorvector instruction.
# Floatingpoint square root vfsqrt.v vd, vs2, vm # Vectorvector square root
14.9. Vector FloatingPoint MIN/MAX Instructions
The vector floatingpoint vfmin
and vfmax
instructions have the
same behavior as the corresponding scalar floatingpoint instructions
in version 2.2 of the RISCV F/D/Q extension.
# Floatingpoint minimum vfmin.vv vd, vs2, vs1, vm # Vectorvector vfmin.vf vd, vs2, rs1, vm # vectorscalar # Floatingpoint maximum vfmax.vv vd, vs2, vs1, vm # Vectorvector vfmax.vf vd, vs2, rs1, vm # vectorscalar
14.10. Vector FloatingPoint SignInjection Instructions
Vector versions of the scalar signinjection instructions. The result
takes all bits except the sign bit from the vector vs2
operands.
vfsgnj.vv vd, vs2, vs1, vm # Vectorvector vfsgnj.vf vd, vs2, rs1, vm # vectorscalar vfsgnjn.vv vd, vs2, vs1, vm # Vectorvector vfsgnjn.vf vd, vs2, rs1, vm # vectorscalar vfsgnjx.vv vd, vs2, vs1, vm # Vectorvector vfsgnjx.vf vd, vs2, rs1, vm # vectorscalar
14.11. Vector FloatingPoint Compare Instructions
These vector FP compare instructions compare two source operands and write the comparison result to a mask register. The destination mask vector is always held in a single vector register, with a layout of elements as described in Section Mask Register Layout.
The compare instructions follow the semantics of the scalar
floatingpoint compare instructions. vmfeq
and vmfne
raise the invalid
operation exception only on signaling NaN inputs. vmflt
, vmfle
, vmfgt
,
and vmfge
raise the invalid operation exception on both signaling and
quiet NaN inputs.
vmfne
writes 1 to the destination element when either
operand is NaN, whereas the other comparisons write 0 when either operand
is NaN.
For all comparison instructions, an illegal instruction exception is raised if the destination vector register overlaps a source vector register group and LMUL > 1.
# Compare equal vmfeq.vv vd, vs2, vs1, vm # Vectorvector vmfeq.vf vd, vs2, rs1, vm # vectorscalar # Compare not equal vmfne.vv vd, vs2, vs1, vm # Vectorvector vmfne.vf vd, vs2, rs1, vm # vectorscalar # Compare less than vmflt.vv vd, vs2, vs1, vm # Vectorvector vmflt.vf vd, vs2, rs1, vm # vectorscalar # Compare less than or equal vmfle.vv vd, vs2, vs1, vm # Vectorvector vmfle.vf vd, vs2, rs1, vm # vectorscalar # Compare greater than vmfgt.vf vd, vs2, rs1, vm # vectorscalar # Compare greater than or equal vmfge.vf vd, vs2, rs1, vm # vectorscalar
Comparison Assembler Mapping Assembler pseudoinstruction va < vb vmflt.vv vd, va, vb, vm va <= vb vmfle.vv vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm va < f vmflt.vf vd, va, f, vm va <= f vmfle.vf vd, va, f, vm va > f vmfgt.vf vd, va, f, vm va >= f vmfge.vf vd, va, f, vm va, vb vector register groups f scalar floatingpoint register
Note

Providing all forms is necessary to correctly handle unordered comparisons for NaNs. 
Note

C99 floatingpoint quiet comparisons can be implemented by masking the signaling comparisons when either input is NaN, as follows. When the comparand is a nonNaN constant, the middle two instructions can be omitted. 
# Example of implementing isgreater() vmfeq.vv v0, va, va # Only set where A is not NaN. vmfeq.vv v1, vb, vb # Only set where B is not NaN. vmand.mm v0, v0, v1 # Only set where A and B are ordered, vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values.
Note

In the above sequence, it is tempting to mask the second vmfeq
instruction and remove the vmand instruction, but this more efficient
sequence incorrectly fails to raise the invalid exception when an
element of va contains a quiet NaN and the corresponding element in
vb contains a signaling NaN.

14.12. Vector FloatingPoint Classify Instruction
This is a unary vectorvector instruction that operates in the same way as the scalar classify instruction.
vfclass.v vd, vs2, vm # Vectorvector
The 10bit mask produced by this instruction is placed in the leastsignificant bits of the result elements. The instruction is only defined for SEW=16b and above, so the result will always fit in the destination elements.
14.13. Vector FloatingPoint Merge Instruction
A vectorscalar floatingpoint merge instruction is provided, which
operates on all body elements, from vstart
up to the current vector
length in vl
regardless of mask value.
The vfmerge.vfm
instruction is always masked (vm=0
).
At elements where the mask value is zero, the first vector operand is
copied to the destination element, otherwise a scalar floatingpoint
register value is copied to the destination element.
vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0[i].LSB ? f[rs1] : vs2[i]
Note

Like the floatingpoint computational instructions, when FLEN > SEW,
vfmerge.vfm substitutes a canonical NaN for f[rs1] if the latter is not
properly NaNboxed.

14.14. Vector FloatingPoint Move Instruction
The vector floatingpoint move instruction splats a floatingpoint scalar
operand to a vector register group. The instruction copies a scalar f
register value to all active elements of a vector register group. This
instruction is always unmasked (vm=1
). The instruction must have the vs2
field set to v0
, with all other values for vs2
reserved.
vfmv.v.f vd, rs1 # vd[i] = f[rs1]
Note

The vfmv.v.f instruction shares the encoding with the vfmerge.vfm
instruction, but with vm=1 and vs2=v0 .

Note

Like the floatingpoint computational instructions, when FLEN > SEW,
vfmv.v.f substitutes a canonical NaN for f[rs1] if the latter is not
properly NaNboxed.

14.15. SingleWidth FloatingPoint/Integer TypeConvert Instructions
Conversion operations are provided to convert to and from floatingpoint values and unsigned and signed integers, where both source and destination are SEW wide.
vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.
The conversions follow the same rules on exceptional conditions as the
scalar conversion instructions. The conversions always use the
dynamic rounding mode in frm
.
14.16. Widening FloatingPoint/Integer TypeConvert Instructions
A set of conversion instructions are provided to convert between narrower integer and floatingpoint datatypes to a type of twice the width.
vfwcvt.xu.f.v vd, vs2, vm # Convert float to doublewidth unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to doublewidth signed integer. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to doublewidth float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to doublewidth float. vfwcvt.f.f.v vd, vs2, vm # Convert singlewidth float to doublewidth float.
These instructions have the same constraints on vector register overlap as other widening instructions (see Widening Vector Arithmetic Instructions).
Note

A doublewidth IEEE floatingpoint value can always represent a singlewidth integer exactly. 
Note

A doublewidth IEEE floatingpoint value can always represent a singlewidth IEEE floatingpoint value exactly. 
Note

A full set of floatingpoint widening conversions are not supported as single instructions, but any widening conversion can be implemented as several doubling steps with equivalent results and no additional exception flags raised. 
14.17. Narrowing FloatingPoint/Integer TypeConvert Instructions
A set of conversion instructions are provided to convert wider integer and floatingpoint datatypes to a type of half the width.
vfncvt.xu.f.w vd, vs2, vm # Convert doublewidth float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert doublewidth float to signed integer. vfncvt.f.xu.w vd, vs2, vm # Convert doublewidth unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert doublewidth signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert doublewidth float to singlewidth float. vfncvt.rod.f.f.w vd, vs2, vm # Convert doublewidth float to singlewidth float, # rounding towards odd.
These instructions have the same constraints on vector register overlap as other narrowing instructions (see Narrowing Vector Arithmetic Instructions).
Note

A full set of floatingpoint widening conversions are not
supported as single instructions. Conversions can be implemented in
a sequence of halving steps. Results are equivalently rounded and
the same exception flags are raised if all but the last halving step
use roundtowardsodd (vfncvt.rod.f.f.w ). Only the final step
should use the desired rounding mode.

Note

An integer value can be halved in width using the narrowing integer shift instructions with a shift amount of 0. 
15. Vector Reduction Operations
Vector reduction operations take a vector register group of elements and a scalar held in element 0 of a vector register, and perform a reduction using some binary operator, to produce a scalar result in element 0 of a vector register. The scalar input and output operands are held in element 0 of a single vector register, not a vector register group, so any vector register can be the scalar source or destination of a vector reduction regardless of LMUL setting.
Note

Reductions read and write the scalar operand and result into element 0 of a vector register to avoid a loss of decoupling with the scalar processor, and to support future polymorphic use with future types not supported in the scalar unit. 
Inactive elements from the source vector register group are excluded from the reduction, but the scalar operand is always included regardless of mask.
The other elements in the destination vector register ( 0 < index < VLEN/SEW) are left unchanged.
If vl
=0, no operation is performed and the destination register is
not updated.
Traps on vector reduction instructions are always reported with a
vstart
of 0. Vector reduction operations raise an illegal
instruction exception if vstart
is nonzero.
The assembler syntax for a reduction operation is vredop.vs
, where
the .vs
suffix denotes the first operand is a vector register group
and the second operand is a scalar stored in element 0 of a vector
register.
15.1. Vector SingleWidth Integer Reduction Instructions
All operands and results of singlewidth reduction instructions have the same SEW width. Overflows wrap around on arithmetic sums.
# Simple reductions, where [*] denotes all active elements: vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] )
15.2. Vector Widening Integer Reduction Instructions
The unsigned vwredsumu.vs
instruction zeroextends the SEWwide
vector elements before summing them, then adds the 2*SEWwidth scalar
element, and stores the result in a 2*SEWwidth scalar element.
The vwredsum.vs
instruction signextends the SEWwide vector
elements before summing them.
# Unsigned sum reduction into doublewidth accumulator vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zeroextend(SEW)) # Signed sum reduction into doublewidth accumulator vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(signextend(SEW))
15.3. Vector SingleWidth FloatingPoint Reduction Instructions
# Simple reductions. vfredosum.vs vd, vs2, vs1, vm # Ordered sum vfredsum.vs vd, vs2, vs1, vm # Unordered sum vfredmax.vs vd, vs2, vs1, vm # Maximum value vfredmin.vs vd, vs2, vs1, vm # Minimum value
15.3.1. Vector Ordered SingleWidth FloatingPoint Sum Reduction
The vfredosum
instruction must sum the floatingpoint values in
element order, starting with the scalar in vs1[0]
that is, it
performs the computation: (((vs1[0] + vs2[0]) + vs2[1]) + …)
, where each addition operates identically to the scalar
floatingpoint instructions in terms of raising exception flags and
generating or propagating special values.
vs2[vl1]
Note

The ordered reduction supports compiler autovectorization, while the unordered FP sum allows for faster implementations. 
When the operation is masked (vm=0
), the maskedoff elements do not
affect the result or the exception flags.
Note

If no elements are active, no additions are performed, so the scalar in
vs1[0] is simply copied to the destination register, without canonicalizing
NaN values and without setting any exception flags. This behavior preserves
the handling of NaNs, exceptions, and rounding when autovectorizing a scalar
summation loop.

15.3.2. Vector Unordered SingleWidth FloatingPoint Sum Reduction
The unordered sum reduction instruction, vfredsum
, provides an
implementation more freedom in performing the reduction.
The implementation can produce a result equivalent to a reduction tree
composed of binary operator nodes, with the inputs being elements from
the source vector register group (vs2
) and the source scalar value
(vs1[0]
). Each operator in the tree accepts two inputs and produces
one result. Each operator can either perform an exact addition, or a
floatingpoint addition according to the RISCV IEEE scalar
floatingpoint specification and with the currently active
floatingpoint dynamic rounding mode.
A node where one input is derived only from elements maskedoff or beyond the
active vector length may either treat that input as IEEE +0.0 of the
appropriate SEW or simply copy the other input to its output. The root node in
the tree must produce an IEEE result of the appropriate SEW. An implementation
is allowed to add an additional IEEE +0.0 to the final result.
The reduction tree structure must be deterministic for a given value
in vtype
and vl
.
Note

As a consequence of this definition, implementations need not propagate
NaN payloads through the reduction tree when no elements are active. In
particular, if no elements are active and the scalar input is NaN,
implementations are permitted to canonicalize the NaN and, if the NaN is
signaling, set the invalid exception flag. Implementations are alternatively
permitted to pass through the original NaN and set no exception flags, as with
vfredosum .

Note

The vfredosum instruction is a valid implementation of the
vfredsum instruction.

15.3.3. Vector SingleWidth Floating Max and Min Reductions
Note

Floatingpoint max and min reductions should return the same final value and raise the same exception flags regardless of operation order. 
15.4. Vector Widening FloatingPoint Reduction Instructions
Widening forms of the sum reductions are provided that read and write a doublewidth reduction result.
# Simple reductions. vfwredosum.vs vd, vs2, vs1, vm # Ordered sum vfwredsum.vs vd, vs2, vs1, vm # Unordered sum
The reduction of the SEWwidth elements is performed as in the
singlewidth reduction case, with the elements in vs2
promoted
to 2*SEW bits before adding to the 2*SEWbit accumulator.
16. Vector Mask Instructions
Several instructions are provided to help operate on mask values held in a vector register.
16.1. Vector MaskRegister Logical Instructions
Vector maskregister logical operations operate on mask registers.
The size of one element in a mask register is SEW/LMUL, so these
instructions all operate on single vector registers regardless of the
setting of the vlmul
field in vtype
. They do not change the value
of vlmul
.
As with other vector instructions, the elements with indices less than
vstart
are unchanged, and vstart
is reset to zero after execution.
Vector mask logical instructions are always unmasked so there are no
inactive elements. Mask elements past vl
, the tail elements, are
unchanged.
Within a mask element, these instructions perform their operations using only the leastsignificant bit of each operand and zeroextend the singlebit result to fill the destination mask element.
vmand.mm vd, vs2, vs1 # vd[i] = vs2[i].LSB && vs1[i].LSB vmnand.mm vd, vs2, vs1 # vd[i] = !(vs2[i].LSB && vs1[i].LSB) vmandnot.mm vd, vs2, vs1 # vd[i] = vs2[i].LSB && !vs1[i].LSB vmxor.mm vd, vs2, vs1 # vd[i] = vs2[i].LSB ^^ vs1[i].LSB vmor.mm vd, vs2, vs1 # vd[i] = vs2[i].LSB  vs1[i].LSB vmnor.mm vd, vs2, vs1 # vd[i] = !(vs2[i[.LSB  vs1[i].LSB) vmornot.mm vd, vs2, vs1 # vd[i] = vs2[i].LSB  !vs1[i].LSB vmxnor.mm vd, vs2, vs1 # vd[i] = !(vs2[i].LSB ^^ vs1[i].LSB)
Several assembler pseudoinstructions are defined as shorthand for common uses of mask logical operations:
vmcpy.m vd, vs => vmand.mm vd, vs, vs # Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits
Note

The vmcpy.m instruction is not called vmmv as elsewhere in the architecture mv implies a bitwise copy without interpreting the bits. The vmcpy.m instruction will clear upper bits of the destination mask register to zero regardless of source values in these bits. 
The set of eight mask logical instructions can generate any of the 16 possibly binary logical functions of the two input masks:
inputs  

0 
0 
1 
1 
src1 
0 
1 
0 
1 
src2 
output  instruction  pseudoinstruction  

0 
0 
0 
0 
vmxor.mm vd, vd, vd 
vmclr.m vd 
1 
0 
0 
0 
vmnor.mm vd, src1, src2 

0 
1 
0 
0 
vmandnot.mm vd, src2, src1 

1 
1 
0 
0 
vmnand.mm vd, src1, src1 
vmnot.m vd, src1 
0 
0 
1 
0 
vmandnot.mm vd, src1, src2 

1 
0 
1 
0 
vmnand.mm vd, src2, src2 
vmnot.m vd, src2 
0 
1 
1 
0 
vmxor.mm vd, src1, src2 

1 
1 
1 
0 
vmnand.mm vd, src1, src2 

0 
0 
0 
1 
vmand.mm vd, src1, src2 

1 
0 
0 
1 
vmxnor.mm vd, src1, src2 

0 
1 
0 
1 
vmand.mm vd, src2, src2 
vmcpy.m vd, src2 
1 
1 
0 
1 
vmornot.mm vd, src2, src1 

0 
0 
1 
1 
vmand.mm vd, src1, src1 
vmcpy.m vd, src1 
1 
0 
1 
1 
vmornot.mm vd, src1, src2 

1 
1 
1 
1 
vmxnor.mm vd, vd, vd 
vmset.m vd 
Note

The vector mask logical instructions are designed to be easily
fused with a following masked vector operation to effectively expand
the number of predicate registers by moving values into v0 before
use.

16.2. Vector mask population count vpopc
vpopc.m rd, vs2, vm
The source operand is a single vector register holding mask register values as described in Section Mask Register Layout.
The vpopc.m
instruction counts the number of mask elements of the
active elements of the vector source mask register that have their
leastsignificant bit set, and writes the result to a scalar x
register.
The operation can be performed under a mask, in which case only the masked elements are counted.
vpopc.m rd, vs2, v0.t # x[rd] = sum_i ( vs2[i].LSB && v0[i].LSB )
Traps on vpopc.m
are always reported with a vstart
of 0. The
vpopc
instruction will raise an illegal instruction exception if
vstart
is nonzero.
16.3. vfirst
findfirstset mask bit
vfirst.m rd, vs2, vm
The vfirst
instruction finds the lowestnumbered active element of
the source mask vector that has its LSB set and writes that element’s
index to a GPR. If no element has an LSB set, 1 is written to the
GPR.
Note

Software can assume that any negative value (highest bit set) corresponds to no element found, as vector lengths will never exceed 2^{(XLEN1)} on any implementation. 
Traps on vfirst
are always reported with a vstart
of 0. The
vfirst
instruction will raise an illegal instruction exception if
vstart
is nonzero.
16.4. vmsbf.m
setbeforefirst mask bit
vmsbf.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsbf.m v2, v3 0 0 0 0 0 0 1 1 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsbf.m v2, v3 0 0 0 0 0 0 0 0 v2 0 0 0 0 0 0 0 0 v3 contents vmsbf.m v2, v3 1 1 1 1 1 1 1 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsbf.m v2, v3, v0.t 0 1 x x x x 1 1 v2 contents
The vmsbf.m
instruction takes a mask register as input and writes
results to a mask register. The instruction writes a 1 to all active
mask elements before the first source element that has a set LSB, then
writes a zero to that element and all following active elements. If
there is no set bit in the source vector, then all active elements in
the destination are written with a 1.
The tail elements in the destination mask register are unchanged.
Traps on vmsbf.m
are always reported with a vstart
of 0. The
vmsbf
instruction will raise an illegal instruction exception if
vstart
is nonzero.
16.5. vmsif.m
setincludingfirst mask bit
The vector mask setincludingfirst instruction is similar to setbeforefirst, except it also includes the element with a set bit.
vmsif.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3 0 0 0 0 0 1 1 1 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsif.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3, v0.t 1 1 x x x x 1 1 v2 contents
The tail elements in the destination mask register are unchanged.
Traps on vmsif.m
are always reported with a vstart
of 0. The
vmsif
instruction will raise an illegal instruction exception if
vstart
is nonzero.
16.6. vmsof.m
setonlyfirst mask bit
The vector mask setonlyfirst instruction is similar to setbeforefirst, except it only sets the first element with a bit set, if any.
vmsof.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsof.m v2, v3 0 0 0 0 0 1 0 0 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsof.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 1 0 1 0 1 0 0 v3 contents vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 contents
The tail elements in the destination mask register are unchanged.
Traps on vmsof.m
are always reported with a vstart
of 0. The
vmsof
instruction will raise an illegal instruction exception if
vstart
is nonzero.
16.7. Example using vector mask instructions
The following is an example of vectorizing a datadependent exit loop.
# char* strcpy(char *dst, const char* src) strcpy: mv a2, a0 # Copy dst li t0, 1 # Infinite AVL loop: vsetvli x0, t0, e8 # Max length vectors of bytes vlbuff.v v1, (a1) # Get src bytes csrr t1, vl # Get number of bytes fetched vmseq.vi v0, v1, 0 # Flag zero bytes vfirst.m a3, v0 # Zero found? add a1, a1, t1 # Bump pointer vmsif.m v0, v0 # Set mask up to and including zero byte. vsb.v v1, (a2), v0.t # Write out bytes add a2, a2, t1 # Bump pointer bltz a3, loop # Zero byte not found, so loop ret # char* strncpy(char *dst, const char* src, size_t n) strncpy: mv a3, a0 # Copy dst loop: vsetvli x0, a2, e8 # Vectors of bytes. vlbuff.v v1, (a1) # Get src bytes vmseq.vi v0, v1, 0 # Flag zero bytes vfirst.m a4, v0 # Zero found? vmsif.m v0, v0 # Set mask up to and including zero byte. vsb.v v1, (a3), v0.t # Write out bytes csrr t1, vl # Get number of bytes fetched sub a2, a2, t1 # Decrement count. bgez a4, zero_tail # Zero remaining bytes. add a1, a1, t1 # Bump pointer add a3, a3, t1 # Bump pointer bnez a2, loop # Anymore? ret zero_tail: vsetvli x0, a2, e8,m8 # Vectors of bytes. vmv.v.i v0, 0 # Splat zero. zero_loop: vsetvli t1, a2, e8,m8 # Vectors of bytes. vsb.v v0, (a3) # Store zero. sub a2, a2, t1 # Decrement count. add a3, a3, t1 # Bump pointer bnez a2, zero_loop # Anymore? ret
16.8. Vector Iota Instruction
The viota.m
instruction reads a source vector mask register and
writes to each element of the destination vector register group the
sum of all the leastsignificant bits of elements in the mask register
whose index is less than the element, e.g., a parallel prefix sum of
the mask values.
This instruction can be masked, in which case only the enabled elements contribute to the sum and only the enabled elements are written.
viota.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 0 0 1 v2 contents viota.m v4, v2 # Unmasked 2 2 2 1 1 1 1 0 v4 result 1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t # Masked 1 1 1 5 1 7 1 0 v4 results
The result value is zeroextended to fill the destination element if SEW is wider than the result. If the result value would overflow the destination SEW, the leastsignificant SEW bits are retained.
Traps on viota.m
are always reported with a vstart
of 0, and
execution is always restarted from the beginning when resuming after a
trap handler. An illegal instruction exception is raised if vstart
is nonzero.
An illegal instruction exception is raised if the destination vector
register group overlaps the source vector mask register. If the
instruction is masked, an illegal instruction exception is issued if
the destination vector register group overlaps v0
.
Note

These constraints exist for two reasons. First, to simplify avoidance of WAR hazards in implementations with temporally long vector registers and no vector register renaming. Second, to enable resuming execution after a trap simpler. 
The viota.m
instruction can be combined with memory scatter
instructions (indexed stores) to perform vector compress functions.
# Compact nonzero elements from input memory array to output memory array # # size_t compact_non_zero(size_t n, const int* in, int* out) # { # size_t i; # size_t count = 0; # int *p = out; # # for (i=0; i<n; i++) # { # const int v = *in++; # if (v != 0) # *p++ = v; # } # # return (size_t) (p  out); # } # # a0 = n # a1 = &in # a2 = &out compact_non_zero: li a6, 0 # Clear count of nonzero elements loop: vsetvli a5, a0, e32,m8 # 32bit integers vlw.v v8, (a1) # Load input vector sub a0, a0, a5 # Decrement number done slli a5, a5, 2 # Multiply by four bytes vmsne.vi v0, v8, 0 # Locate nonzero values add a1, a1, a5 # Bump input pointer vpopc.m a5, v0 # Count number of elements set in v0 viota.m v16, v0 # Get destination offsets of active elements add a6, a6, a5 # Accumulate number of elements vsll.vi v16, v16, 2, v0.t # Multiply offsets by four bytes slli a5, a5, 2 # Multiply number of nonzero elements by four bytes vsuxw.v v8, (a2), v16, v0.t # Scatter using scaled viota results under mask add a2, a2, a5 # Bump output pointer bnez a0, loop # Any more? mv a0, a6 # Return count ret
16.9. Vector Element Index Instruction
The vid.v
instruction writes each element’s index to the
destination vector register group, from 0 to vl
1.
vid.v vd, vm # Write element ID to destination.
The instruction can be masked.
The vs2
field of the instruction must be set to v0
, otherwise the
encoding is reserved.
The result value is zeroextended to fill the destination element if SEW is wider than the result. If the result value would overflow the destination SEW, the leastsignificant SEW bits are retained.
Note

This constraint is to avoid WAR hazards in long vector implementations without register renaming, and to support restart. 
Note

Microarchitectures can implement vid.v instruction using the
same datapath as viota.m but with an implicit set mask source.

17. Vector Permutation Instructions
A range of permutation instructions are provided to move elements around within the vector registers.
17.1. Integer Scalar Move Instructions
The integer scalar read/write instructions transfer a single
value between a scalar x
register and element 0 of a vector
register. The instructions ignore LMUL and vector register groups.
vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0)
The vmv.x.s
instruction copies a single SEWwide element from index 0 of the
source vector register to a destination integer register. If SEW > XLEN, the
leastsignificant XLEN bits are transferred and the upper SEWXLEN bits are
ignored. If SEW < XLEN, the value is signextended to XLEN bits.
The vmv.s.x
instruction copies the scalar integer register to element 0 of
the destination vector register. If SEW < XLEN, the leastsignificant bits
are copied and the upper XLENSEW bits are ignored. If SEW > XLEN, the value
is signextended to SEW bits. The other elements in the destination vector
register ( 0 < index < VLEN/SEW) are unchanged. If vstart
≥ vl
, no
operation is performed and the destination register is not updated.
Note

As a consequence, when vl =0, no elements are updated in the
destination vector register group, regardless of vstart .

The encodings corresponding to the masked versions (vm=0
) of vmv.x.s
and vmv.s.x
are reserved.
17.2. FloatingPoint Scalar Move Instructions
The floatingpoint scalar read/write instructions transfer a single
value between a scalar f
register and element 0 of a vector
register. The instructions ignore LMUL and vector register groups.
vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0) vfmv.s.f vd, rs1 # vd[0] = f[rs1] (vs2=0)
The vfmv.f.s
instruction copies a single SEWwide element from index
0 of the source vector register to a destination scalar floatingpoint
register. If SEW > FLEN, vfmv.f.s
substitutes an FLENbit canonical
NaN if the element value is not correctly NaNboxed for FLEN. If SEW
< FLEN, the value is NaNboxed (1extended) to FLEN bits.
The vfmv.s.f
instruction copies the scalar floatingpoint register
to element 0 of the destination vector register. If SEW < FLEN and
the value is not correctly NaNboxed for SEW bits, an SEWbit
canonical NaN is substituted. If SEW > FLEN, the value is NaNboxed
(1extended) to SEW bits. The other elements in the destination
vector register ( 0 < index < VLEN/SEW) are unchanged. If vstart
≥ vl
, no operation is performed and the destination register is
not updated.
Note

As a consequence, when vl =0, no elements are updated in the
destination vector register group, regardless of vstart .

The encodings corresponding to the masked versions (vm=0
) of vfmv.f.s
and vfmv.s.f
are reserved.
17.3. Vector Slide Instructions
The slide instructions move elements up and down a vector register group.
Note

The slide operations can be implemented much more efficiently
than using the arbitrary register gather instruction. Implementations
may optimize certain OFFSET values for vslideup and vslidedown .
In particular, powerof2 offsets may operate substantially faster
than other offsets.

For all of the vslideup
, vslidedown
, vslide1up
, and
vslide1down
instructions, if vstart
≥ vl
, the instruction performs no
operation and leaves the destination vector register unchanged.
Note

As a consequence, when vl =0, no elements are updated in the
destination vector register group, regardless of vstart .

The slide instructions may be masked, with mask element i controlling whether destination element i is written.
17.3.1. Vector Slideup Instructions
vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] vslideup.vi vd, vs2, uimm[4:0], vm # vd[i+uimm] = vs2[i]
For vslideup
, the value in vl
specifies the maximum number of destination
elements that are written. The start index (OFFSET) for the
destination can be either specified using an unsigned integer in the
x
register specified by rs1
, or a 5bit immediate treated as an
unsigned 5bit quantity.
If XLEN > SEW, OFFSET is not truncated to SEW bits.
Destination elements OFFSET through vl
1 are written if unmasked and
if OFFSET < vl
.
vslideup behavior for destination elements OFFSET is amount to slideup, either from x register or a 5bit immediate 0 < i < max(vstart, OFFSET) Unchanged max(vstart, OFFSET) <= i < vl vd[i] = vs2[iOFFSET] if mask enabled, unchanged if not vl <= i < VLMAX Tail elements, unchanged
The destination vector register group for vslideup
cannot overlap
the vector register group of the source vector register group or the
mask register, otherwise an illegal instruction exception is raised.
Note

The nonoverlap constraint avoids WAR hazards on the
input vectors during execution, and enables restart with nonzero
vstart .

17.3.2. Vector Slidedown Instructions
vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] vslidedown.vi vd, vs2, uimm[4:0], vm # vd[i] = vs2[i+uimm]
For vslidedown
, the value in vl
specifies the number of
destination elements that are written.
The start index (OFFSET) for the source can be either specified
using an unsigned integer in the x
register specified by rs1
, or a
5bit immediate treated as an unsigned 5bit quantity.
If XLEN > SEW, OFFSET is not truncated to SEW bits.
vslidedown behavior for source elements for element i in slide 0 <= i+OFFSET < VLMAX Read vs2[i+OFFSET] VLMAX <= i+OFFSET Read as 0 vslidedown behavior for destination element i in slide 0 < i < vstart Unchanged vstart <= i < vl Updated if mask enabled, unchanged if not vl <= i < VLMAX Unchanged
The destination vector register group cannot overlap the mask register if LMUL>1, otherwise an illegal instruction exception is raised.
17.3.3. Vector Slide1up
Variants of slide are provided that only move by one element but which also allow a scalar integer value to be inserted at the vacated element position.
vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i]
The vslide1up
instruction places the x
register argument at
location 0 of the destination vector register group, provided that
element 0 is active, otherwise the destination element is unchanged.
If XLEN < SEW, the value is signextended to SEW bits. If XLEN > SEW,
the leastsignificant bits are copied over and the high SEWXLEN bits
are ignored.
The remaining active vl
1 elements are copied over from index i in
the source vector register group to index i+1 in the destination
vector register group.
The vl
register specifies how many of the destination vector
register elements are written with source values, and all tail
elements are unchanged.
vslide1up behavior i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if mask enabled, unchanged if not max(vstart, 1) <= i < vl vd[i] = vs2[i1] if mask enabled, unchanged if not vl <= i < VLMAX unchanged
The vslide1up
instruction requires that the destination vector
register group does not overlap the source vector register group or
the mask register. Otherwise, an illegal instruction exception is
raised.
17.3.4. Vector Slide1down Instruction
The vslide1down
instruction copies the first vl
1 active elements
values from index i+1 in the source vector register group to index
i in the destination vector register group.
The vl
register specifies how many of the destination vector
register elements are written with source values, and all tail
elements are unchanged.
vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl1]=x[rs1]
The vslide1down
instruction places the x
register argument at
location vl
1 in the destination vector register, provided that
element vl1
is active, otherwise the destination element is
unchanged. If XLEN < SEW, the value is signextended to SEW bits. If
XLEN > SEW, the leastsignificant bits are copied over and the high
SEWXLEN bits are ignored.
vslide1down behavior i < vstart unchanged vstart <= i < vl1 vd[i] = vs2[i+1] if mask enabled, unchanged if not vstart <= i = vl1 vd[vl1] = x[rs1] if mask enabled, unchanged if not vl <= i < VLMAX unchanged
The destination vector register group cannot overlap the source mask register if LMUL>1, otherwise an illegal instruction exception is raised.
Note

The vslide1down instruction can be used to load values into a
vector register without using memory and without disturbing other
vector registers. This provides a path for debuggers to modify the
contents of a vector register, albeit slowly, with multiple repeated
vslide1down invocations.

17.4. Vector Register Gather Instruction
The vector register gather instruction reads elements from a first
source vector register group at locations given by a second source
vector register group. The index values in the second vector are
treated as unsigned integers. The source vector can be read at any
index < VLMAX regardless of vl
. The number of elements to write to
the destination register is given by vl
, and elements past vl
in
the destination are unchanged. The operation can be masked.
vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
If the element indices are out of range ( vs1[i]
≥ VLMAX )
then zero is returned for the element value.
Vectorscalar and vectorimmediate forms of the register gather are
also provided. These read one element from the source vector at the
given index, and write this value to the vl
elements at the start of
the destination vector register. The index value in the scalar register
and the immediate are treated as unsigned integers.
If XLEN > SEW, the index value is not truncated to SEW bits.
Note

These forms allow any vector element to be "splatted" to an entire vector. 
vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]
For any vrgather
instruction, the destination vector register group
cannot overlap with the source vector register groups, including the
mask register if the operation is masked, otherwise an illegal
instruction exception is raised.
Note

When SEW=8, vrgather.vv can only reference vector elements 0255.

17.5. Vector Compress Instruction
The vector compress instruction allows elements selected by a vector mask register from a source vector register group to be packed into contiguous elements at the start of the destination vector register group.
vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled
The vector mask register specified by vs1
indicates which of the
first vl
elements of vector register group vs2
should be extracted
and packed into contiguous elements at the beginning of vector
register vd
. Any remaining elements of vd
are unchanged.
Example use of vcompress instruction 1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2
vcompress
is encoded as an unmasked instruction (vm=1
). The equivalent
masked instruction (vm=0
) is reserved.
The destination vector register group cannot overlap the source vector register group or the source vector mask register, otherwise an illegal instruction exception is raised.
A trap on a vcompress
instruction is always reported with a
vstart
of 0. Executing a vcompress
instruction with a nonzero
vstart
raises an illegal instruction exception.
Note

Although possible, vcompress is one of the more difficult
instructions to restart with a nonzero vstart , so assumption is
implementations will choose not do that but will instead restart from
element 0. This does mean elements in destination register after
vstart will already have been updated.

17.6. Whole Vector Register Move
The vmv<nf>r.v
instructions copy whole vector registers (i.e., all
VLEN bits) ignoring the current settings of the vl
and vtype
register, and can copy whole vector register groups.
Note

These instructions are intended to aid compilers to shuffle
vector registers without needing to know or change vl or vtype .

The instruction is encoded as an OPIVI instruction. The number of
vector registers to copy is encoded in the low three bits of the
simm
field using the same encoding as the nf
field for memory
instructions. The upper two bits of simm
field must be zero, with
other encodings reserved. The value in nf
must be correspond to 1,
2, 4, or 8 registers.
Note

A future extension may support other numbers of registers to be
moved, but currently the values of nf corresponding to 3, 5, 6, 7
are reserved.

Note

The instruction uses the same funct6 encoding as the vsmul
instruction but with an immediate operand, and only the unmasked
version (vm=1 ). This encoding is chosen as it is close to the
related vmerge encoding, and it is unlikely the vsmul instruction
would benefit from an immediate form.

vmv<nf>r.v vd, vs2 # General form vmv1r.v v1, v2 # Copy v1=v2 vmv2r.v v10, v12 # Copy v10=v12; v11=v13 vmv4r.v v4, v8 # Copy v4=v8; v5=v9; v6=v10; v7=v11 vmv8r.v v0, v8 # Copy v0=v8; v1=v9; ...; v7=v15
The source and destination vector register numbers must be aligned appropriately for the vector register group size.
Note

A future extension may relax the vector register alignment restrictions. 
Note

If vd is equal to vs2 the instruction is a NOP.

18. Exception Handling
On a trap during a vector instruction (caused by either a synchronous
exception or an asynchronous interrupt), the existing *epc
CSR is
written with a pointer to the errant vector instruction, while the
vstart
CSR contains the element index that caused the trap to be
taken.
Note

We chose to add a vstart CSR to allow resumption of a
partially executed vector instruction to reduce interrupt latencies
and to simplify forwardprogress guarantees. This is similar to the
scheme in the IBM 3090 vector facility. To ensure forward progress
without the vstart CSR, implementations would have to guarantee an
entire vector instruction can always complete atomically without
generating a trap. This is particularly difficult to ensure in the
presence of strided or scatter/gather operations and demandpaged
virtual memory.

18.1. Precise vector traps
Precise vector traps require that:

all instructions older than the trapping vector instruction have committed their results

no instructions newer than the trapping vector instruction have altered architectural state

any operations within the trapping vector instruction affecting result elements preceding the index in the
vstart
CSR have committed their results 
no operations within the trapping vector instruction affecting elements at or following the
vstart
CSR have altered architectural state except if restarting and completing the affected vector instruction will recover the correct state.
We relax the last requirement to allow elements following vstart
to
have been updated at the time the trap is reported, provided that
reexecuting the instruction from the given vstart
will correctly
overwrite those elements.
Note

We assume most supervisormode environments will require precise vector traps. 
Except where noted above, vector instructions are allowed to overwrite
their inputs, and so in most cases, the vector instruction restart
must be from the vstart
location. However, there are a number of
cases where this overwrite is prohibited to enable execution of the
the vector instructions to be idempotent and hence restartable from
any location.
18.2. Imprecise vector traps
Imprecise vector traps are traps that are not precise. In particular,
instructions newer than *epc
may have committed results, and
instructions older than *epc
may have not completed execution.
Imprecise traps are primarily intended to be used in situations where
reporting an error and terminating execution is the appropriate
response.
Note

A platform might specify that interrupts are precise while other traps are imprecise. We assume many embedded platforms will only generate imprecise traps for vector instructions on fatal errors, so do not require resumable traps. 
18.3. Selectable precise/imprecise traps
Some platforms may choose to provide a privileged mode bit to select between precise and imprecise vector traps. Imprecise mode would run at highperformance but possibly make it difficult to discern error causes, while precise mode would run more slowly, but support debugging of errors albeit with a possibility of not experiencing the same errors as in imprecise mode.
18.4. Swappable traps
Another trap mode can support swappable state in the vector unit, where on a trap, special instructions can save and restore the vector unit microarchitectural state, to allow execution to continue correctly around imprecise traps.
This mechanism is not defined in the base vector ISA.
19. Divided Element Extension ('Zvediv')
Note

The EDIV extension is currently not planned to be part of the base "V" extension, and will change substantially from the current sketch. 
The divided element extension allows each element to be treated as a packed subvector of narrower elements. This provides efficient support for some forms of narrowwidth and mixedwidth arithmetic, and also to allow outerloop vectorization of short vector and matrix operations. In addition to modifying the behavior of some existing instructions, a few new instructions are provided to operate on vectors when EDIV > 1.
The divided element extension adds a twobit field, vediv[1:0]
to
the vtype
register.
Bits  Name  Description 

XLEN1 
vill 
Illegal value if set 
XLEN2:7 
Reserved (write 0) 

6:5 
vediv[1:0] 
Used by EDIV extension 
4:2 
vsew[2:0] 
Standard element width (SEW) setting 
1:0 
vlmul[1:0] 
Vector register group multiplier (LMUL) setting 
The vediv
field encodes the number of ways, EDIV, into which each
SEWbit element is subdivided into equal subelements. A vector
register group is now considered to hold a vector of subvectors.
vediv [1:0]  Division EDIV  

0 
0 
1 
(undivided, as in base) 
0 
1 
2 
two equal subelements 
1 
0 
4 
four equal subelements 
1 
1 
8 
eight equal subelements 
SEW 
EDIV 
Subelement 
Integer accumulator 
FP sum/dot accumulator 

sum 
dot 
FLEN=32 
FLEN=64 
FLEN=128 

8b 
2 
4b 
8b 
8b 
 
 
 
8b 
4 
2b 
8b 
8b 
 
 
 
8b 
8 
1b 
8b 
8b 
 
 
 
16b 
2 
8b 
16b 
16b 
 
 
 
16b 
4 
4b 
8b 
16b 
 
 
 
16b 
8 
2b 
8b 
8b 
 
 
 
32b 
2 
16b 
32b 
32b 
32b 
32b 
32b 
32b 
4 
8b 
16b 
32b 
 
 
 
32b 
8 
4b 
8b 
16b 
 
 
 
64b 
2 
32b 
64b 
64b 
32b 
64b 
64b 
64b 
4 
16b 
32b 
64b 
32b 
32b 
32b 
64b 
8 
8b 
16b 
32b 
 
 
 
128b 
2 
64b 
128b 
128b 
32b 
64b 
128b 
128b 
4 
32b 
64b 
128b 
32b 
64b 
64b 
128b 
8 
16b 
32b 
64b 
32b 
32b 
32b 
256b 
2 
128b 
256b 
256b 
32b 
64b 
128b 
256b 
4 
64b 
128b 
256b 
32b 
64b 
128b 
256b 
8 
32b 
64b 
128b 
32b 
64b 
64b 
Each implementation defines a minimum size for a subelement, SELEN, which must be at most 8 bits.
Note

While SELEN is a fourth implementationspecific parameter, values smaller than 8 would be considered an additional extension. 
19.1. Instructions not affected by EDIV
The vector start register vstart
and exception reporting continue to
work as before.
The vector length vl
control and vector masking continue to operate
at the element level.
Vector masking continues to operate at the element level, so subelements cannot be individually masked.
Note

SEW can be changed dynamically to enabled perelement masking for subelements of 8 bits and greater. 
Vector load/store and AMO instructions are unaffected by EDIV, and continue to move whole elements.
Vector mask logical operations are unchanged by EDIV setting, and continue to operate on vector registers containing element masks.
Vector mask population count (vpopc
), findfirst and related
instructions (vfirst
, vmsbf
, vmsif
, vmsof
), iota (viota
),
and element index (vid
) instructions are unaffected by EDIV.
Vector integer bit insert/extract, and integer and floatingpoint scalar move instruction are unaffected by EDIV.
Vector slideup/slidedown are unaffected by EDIV.
Vector compress instructions are unaffected by EDIV.
19.2. Instructions Affected by EDIV
19.2.1. Regular Vector Arithmetic Instructions under EDIV
Most vector arithmetic operations are modified to operate on the
individual subelements, so effective SEW is SEW/EDIV and effective
vector length is vl
* EDIV. For example, a vector add of 32bit
elements with a vl
of 5 and EDIV of 4, operates identically to a
vector add of 8bit elements with a vector length of 20.
vsetvli t0, a0, e32,m1,d4 # Vectors of 32bit elements, divided into byte subelements vadd.vv v1,v2,v3 # Performs a vector of 4*vl 8bit additions. vsll.vx v1,v2,x1 # Performs a vector of 4*vl 8bit shifts.
19.2.2. Vector Add with Carry/Subtract with Borrow Reserved under EDIV>1
For EDIV > 1, vadc
, vmadc
, vsbc
, vmsbc
are reserved.
19.2.3. Vector Reduction Instructions under EDIV
Vector singlewidth integer sum reduction instructions are reserved under EDIV>1. Other vector singlewidth reductions and vector widening integer sum reduction instructions now operate independently on all elements in a vector, reducing subelement values within an element to an elementwide result.
The scalar input is taken from the leastsignificant bits of the second operand, with the number of bits equal to the number of significant result bits (i.e., for sum and dot reductions, the number of bits are given in table above, for nonsum and nondot reductions, equal to the element size).
# Sum each subvector of four bytes into a 16bit result. vsetvli t0, a0, e32,d4 # Vectors of 32bit elements, divided into byte subelements vwredsum.vs v1, v2, v3 # v1[i][15:0] = v2[i][31:24] + v2[i][23:16] # + v2[i][15:8] + v2[i][7:0] + v3[i][15:0] # Find maximum among subelements vredmax.vs v5, v6, v7 # v5[i][7:0] = max(v6[i][31:24], v6[i][23:16], # v6[i][15:8], v6[i][7:0], v7[i][7:0])
Integer subelement nonsum reductions produce a final result that is max(8,SEW/EDIV) bits wide, sign or zeroextended to full SEW if necessary.
Integer subelement widening sum reductions produce a final result that is max(8,min(SEW,2*SEW/EDIV)) bits wide, sign or zeroextended to full SEW if necessary.
Singlewidth floatingpoint reductions produce a final result that is SEW/EDIV bits wide.
Widening floatingpoint sum reductions produce a final result that is min(2*SEW/EDIV,FLEN) bits wide, NaNboxed to the full SEW width if necessary.
19.2.4. Vector Register Gather Instructions under EDIV
Vector register gather instructions under nonzero EDIV only gather subelements within the element. The source and index values are interpreted as relative to the enclosing element only. Index values ≥ EDIV write a zero value into the result subelement.
   SEW = 32b, EDIV=4 7 6 5 4 3 2 1 0 bytes d e a d b e e f v1 0 1 9 2 0 2 3 2 v2 vrgather.vv v3, v1, v2 d a 0 e f e b e v3 vrgather.vi v4, v1, 1 a a a a e e e e v4
Note

Vector register gathers with scalar or immediate arguments can "splat" values across subelements within an element. 
Note

Implementations can provide fast implementations of register gathers constrained within a single element width. 
19.3. Vector Integer DotProduct Instruction
The integer dotproduct reduction vdot.vv
performs an elementwise
multiplication between the source subelements then accumulates the
results into the destination vector element. Note the assembler syntax
uses a .vv
suffix since both inputs are vectors of elements.
Subelement integer dot reductions produce a final result that is max(8,min(SEW,4*SEW/EDIV)) bits wide, sign or zeroextended to full SEW if necessary.
# Unsigned dotproduct vdotu.vv vd, vs2, vs1, vm # Vectorvector # Signed dotproduct vdot.vv vd, vs2, vs1, vm # Vectorvector
# Dot product, SEW=32, EDIV=1 vdot.vv vd, vs2, vs1, vm # vd[i][31:0] += vs2[i][31:0] * vs1[i][31:0] # Dot product, SEW=32, EDIV=2 vdot.vv vd, vs2, vs1, vm # vd[i][31:0] += vs2[i][31:16] * vs1[i][31:16] + vs2[i][15:0] * vs1[i][15:0] # Dot product, SEW=32, EDIV=4 vdot.vv vd, vs2, vs1, vm # vd[i][31:0] += vs2[i][31:24] * vs1[i][31:24] + vs2[i][23:16] * vs1[i][23:16] + vs2[i][15:8] * vs1[i][15:8] + vs2[i][7:0] * vs1[i][7:0]
19.4. Vector FloatingPoint Dot Product Instruction
The floatingpoint dotproduct reduction vfdot.vv
performs an elementwise
multiplication between the source subelements then accumulates the
results into the destination vector element. Note the assembler syntax
uses a .vv
suffix since both inputs are vectors of elements.
# Signed dotproduct vfdot.vv vd, vs2, vs1, vm # Vectorvector
# Dot product. SEW=32, EDIV=2 vfdot.vv vd, vs2, vs1, vm # vd[i][31:0] += vs2[i][31:16] * vs1[i][31:16] + vs2[i][15:0] * vs1[i][15:0] # Floatingpoint subvectors of two halfprecision floats packed into 32bit elements. vsetvli t0, a0, e32,m1,d2 # Vectors of 32bit elements, divided into 16b subelements vfdot.vv v1, v2, v3 # v1[i][31:0] += v2[i][31:16]*v3[i][31:16] + v2[i][16:0]*v3[i][16:0] # Floatingpoint subvectors of four halfprecision floats packed into 64bit elements. vsetvli t0, a0, e64,m1,d4 # Vectors of 64bit elements, divided into 16b subelements vfdot.vv v1, v2, v3 # v1[i][31:0] += v2[i][31:16]*v3[i][31:16] + v2[i][16:0]*v3[i][16:0] + # v2[i][63:48]*v3[i][63:48] + v2[i][47:32]*v3[i][47:32]; # v1[i][63:32] = ~0 (NaN boxing)
20. Vector Instruction Listing
Integer  Integer  FP  

funct3 
funct3 
funct3 

OPIVV 
V 
OPMVV 
V 
OPFVV 
V 

OPIVX 
X 
OPMVX 
X 
OPFVF 
F 

OPIVI 
I 
funct6  funct6  funct6  

000000 
V 
X 
I 
vadd 
000000 
V 
vredsum 
000000 
V 
F 
vfadd 

000001 
000001 
V 
vredand 
000001 
V 
vfredsum 

000010 
V 
X 
vsub 
000010 
V 
vredor 
000010 
V 
F 
vfsub 

000011 
X 
I 
vrsub 
000011 
V 
vredxor 
000011 
V 
vfredosum 

000100 
V 
X 
vminu 
000100 
V 
vredminu 
000100 
V 
F 
vfmin 

000101 
V 
X 
vmin 
000101 
V 
vredmin 
000101 
V 
vfredmin 

000110 
V 
X 
vmaxu 
000110 
V 
vredmaxu 
000110 
V 
F 
vfmax 

000111 
V 
X 
vmax 
000111 
V 
vredmax 
000111 
V 
vfredmax 

001000 
001000 
V 
X 
vaaddu 
001000 
V 
F 
vfsgnj 

001001 
V 
X 
I 
vand 
001001 
V 
X 
vaadd 
001001 
V 
F 
vfsgnjn 
001010 
V 
X 
I 
vor 
001010 
V 
X 
vasubu 
001010 
V 
F 
vfsgnjx 
001011 
V 
X 
I 
vxor 
001011 
V 
X 
vasub 
001011 

001100 
V 
X 
I 
vrgather 
001100 
001100 

001101 
001101 
001101 

001110 
X 
I 
vslideup 
001110 
X 
vslide1up 
001110 

001111 
X 
I 
vslidedown 
001111 
X 
vslide1down 
001111 
funct6  funct6  funct6  

010000 
V 
X 
I 
vadc 
010000 
V 
VWXUNARY0 
010000 
V 
VWFUNARY0 

010000 
X 
VRXUNARY0 
010000 
F 
VRFUNARY0 

010001 
V 
X 
I 
vmadc 
010001 
010001 

010010 
V 
X 
vsbc 
010010 
010010 

010011 
V 
X 
vmsbc 
010011 
010011 

010100 
010100 
V 
VMUNARY0 
010100 

010101 
010101 
010101 

010110 
010110 
010110 

010111 
V 
X 
I 
vmerge/vmv 
010111 
V 
vcompress 
010111 
F 
vfmerge.vf/vfmv 

011000 
V 
X 
I 
vmseq 
011000 
V 
vmandnot 
011000 
V 
F 
vmfeq 

011001 
V 
X 
I 
vmsne 
011001 
V 
vmand 
011001 
V 
F 
vmfle 

011010 
V 
X 
vmsltu 
011010 
V 
vmor 
011010 

011011 
V 
X 
vmslt 
011011 
V 
vmxor 
011011 
V 
F 
vmflt 

011100 
V 
X 
I 
vmsleu 
011100 
V 
vmornot 
011100 
V 
F 
vmfne 

011101 
V 
X 
I 
vmsle 
011101 
V 
vmnand 
011101 
F 
vmfgt 

011110 
X 
I 
vmsgtu 
011110 
V 
vmnor 
011110 

011111 
X 
I 
vmsgt 
011111 
V 
vmxnor 
011111 
F 
vmfge 
funct6  funct6  funct6  

100000 
V 
X 
I 
vsaddu 
100000 
V 
X 
vdivu 
100000 
V 
F 
vfdiv 
100001 
V 
X 
I 
vsadd 
100001 
V 
X 
vdiv 
100001 
F 
vfrdiv 

100010 
V 
X 
vssubu 
100010 
V 
X 
vremu 
100010 
V 
VFUNARY0 

100011 
V 
X 
vssub 
100011 
V 
X 
vrem 
100011 
V 
VFUNARY1 

100100 
100100 
V 
X 
vmulhu 
100100 
V 
F 
vfmul 

100101 
V 
X 
I 
vsll 
100101 
V 
X 
vmul 
100101 

100110 
100110 
V 
X 
vmulhsu 
100110 

100111 
V 
X 
vsmul 
100111 
V 
X 
vmulh 
100111 
F 
vfrsub 

I 
vmv<nf>r 

101000 
V 
X 
I 
vsrl 
101000 
101000 
V 
F 
vfmadd 

101001 
V 
X 
I 
vsra 
101001 
V 
X 
vmadd 
101001 
V 
F 
vfnmadd 
101010 
V 
X 
I 
vssrl 
101010 
101010 
V 
F 
vfmsub 

101011 
V 
X 
I 
vssra 
101011 
V 
X 
vnmsub 
101011 
V 
F 
vfnmsub 
101100 
V 
X 
I 
vnsrl 
101100 
101100 
V 
F 
vfmacc 

101101 
V 
X 
I 
vnsra 
101101 
V 
X 
vmacc 
101101 
V 
F 
vfnmacc 
101110 
V 
X 
I 
vnclipu 
101110 
101110 
V 
F 
vfmsac 

101111 
V 
X 
I 
vnclip 
101111 
V 
X 
vnmsac 
101111 
V 
F 
vfnmsac 
funct6  funct6  funct6  

110000 
V 
vwredsumu 
110000 
V 
X 
vwaddu 
110000 
V 
F 
vfwadd 

110001 
V 
vwredsum 
110001 
V 
X 
vwadd 
110001 
V 
vfwredsum 

110010 
110010 
V 
X 
vwsubu 
110010 
V 
F 
vfwsub 

110011 
110011 
V 
X 
vwsub 
110011 
V 
vfwredosum 

110100 
110100 
V 
X 
vwaddu.w 
110100 
V 
F 
vfwadd.w 

110101 
110101 
V 
X 
vwadd.w 
110101 

110110 
110110 
V 
X 
vwsubu.w 
110110 
V 
F 
vfwsub.w 

110111 
110111 
V 
X 
vwsub.w 
110111 

111000 
V 
vdotu 
111000 
V 
X 
vwmulu 
111000 
V 
F 
vfwmul 

111001 
V 
vdot 
111001 
111001 
V 
vfdot 

111010 
111010 
V 
X 
vwmulsu 
111010 

111011 
111011 
V 
X 
vwmul 
111011 

111100 
V 
X 
vqmaccu 
111100 
V 
X 
vwmaccu 
111100 
V 
F 
vfwmacc 

111101 
V 
X 
vqmacc 
111101 
V 
X 
vwmacc 
111101 
V 
F 
vfwnmacc 

111110 
X 
vqmaccus 
111110 
X 
vwmaccus 
111110 
V 
F 
vfwmsac 

111111 
V 
X 
vqmaccsu 
111111 
V 
X 
vwmaccsu 
111111 
V 
F 
vfwnmsac 
vs2  

00000 
vmv.s.x 
vs1  

00000 
vmv.x.s 
10000 
vpopc 
10001 
vfirst 
vs2  

00000 
vfmv.s.f 
vs1  

00000 
vfmv.f.s 
vs1  name 

singlewidth converts 

00000 
vfcvt.xu.f.v 
00001 
vfcvt.x.f.v 
00010 
vfcvt.f.xu.v 
00011 
vfcvt.f.x.v 
widening converts 

01000 
vfwcvt.xu.f.v 
01001 
vfwcvt.x.f.v 
01010 
vfwcvt.f.xu.v 
01011 
vfwcvt.f.x.v 
01100 
vfwcvt.f.f.v 
narrowing converts 

10000 
vfncvt.xu.f.w 
10001 
vfncvt.x.f.w 
10010 
vfncvt.f.xu.w 
10011 
vfncvt.f.x.w 
10100 
vfncvt.f.f.w 
10101 
vfncvt.rod.f.f.w 
vs1  name 

00000 
vfsqrt.v 
10000 
vfclass.v 
vs1  

00001 
vmsbf 
00010 
vmsof 
00011 
vmsif 
10000 
viota 
10001 
vid 
Appendix A: Vector Assembly Code Examples
The following are provided as nonnormative text to help explain the vector ISA.
A.1. Vectorvector add example
# vectorvector add routine of 32bit integers # void vvaddint32(size_t n, const int*x, const int*y, int*z) # { for (size_t i=0; i<n; i++) { z[i]=x[i]+y[i]; } } # # a0 = n, a1 = x, a2 = y, a3 = z # Nonvector instructions are indented vvaddint32: vsetvli t0, a0, e32 # Set vector length based on 32bit vectors vlw.v v0, (a1) # Get first vector sub a0, a0, t0 # Decrement number done slli t0, t0, 2 # Multiply number done by 4 bytes add a1, a1, t0 # Bump pointer vlw.v v1, (a2) # Get second vector add a2, a2, t0 # Bump pointer vadd.vv v2, v0, v1 # Sum vectors vsw.v v2, (a3) # Store result add a3, a3, t0 # Bump pointer bnez a0, vvaddint32 # Loop back ret # Finished
A.2. Example with mixedwidth mask and compute.
# Code using one width for predicate and different width for masked # compute. # int8_t a[]; int32_t b[], c[]; # for (i=0; i<n; i++) { b[i] = (a[i] < 5) ? c[i] : 1; } # # Mixedwidth code that keeps SEW/LMUL=8 loop: vsetvli a4, a0, e8,m1 # Byte vector for predicate calc vlb.v v1, (a1) # Load a[i] add a1, a1, a4 # Bump pointer. vmslt.vi v0, v1, 5 # a[i] < 5? vsetvli x0, a0, e32,m4 # Vector of 32bit values. sub a0, a0, a4 # Decrement count vmv.v.i v4, 1 # Splat immediate to destination vlw.v v4, (a3), v0.t # Load requested elements of C. sll t1, a4, 2 add a3, a3, t1 # Bump pointer. vsw.v v4, (a2) # Store b[i]. add a2, a2, t1 # Bump pointer. bnez a0, loop # Any more?
A.3. Memcpy example
# void *memcpy(void* dest, const void* src, size_t n) # a0=dest, a1=src, a2=n # memcpy: mv a3, a0 # Copy destination loop: vsetvli t0, a2, e8,m8 # Vectors of 8b vlb.v v0, (a1) # Load bytes add a1, a1, t0 # Bump pointer sub a2, a2, t0 # Decrement count vsb.v v0, (a3) # Store bytes add a3, a3, t0 # Bump pointer bnez a2, loop # Any more? ret # Return
A.4. Conditional example
# (int16) z[i] = ((int8) x[i] < 5) ? (int16) a[i] : (int16) b[i]; # # Fixed 16b SEW: loop: vsetvli t0, a0, e16 # Use 16b elements. vlb.v v0, (a1) # Get x[i], signextended to 16b sub a0, a0, t0 # Decrement element count add a1, a1, t0 # x[i] Bump pointer vmslt.vi v0, v0, 5 # Set mask in v0 slli t0, t0, 1 # Multiply by 2 bytes vlh.v v1, (a2), v0.t # z[i] = a[i] case vmnot.m v0, v0 # Invert v0 add a2, a2, t0 # a[i] bump pointer vlh.v v1, (a3), v0.t # z[i] = b[i] case add a3, a3, t0 # b[i] bump pointer vsh.v v1, (a4) # Store z add a4, a4, t0 # b[i] bump pointer bnez a0, loop
A.5. SAXPY example
# void # saxpy(size_t n, const float a, const float *x, float *y) # { # size_t i; # for (i=0; i<n; i++) # y[i] = a * x[i] + y[i]; # } # # register arguments: # a0 n # fa0 a # a1 x # a2 y saxpy: vsetvli a4, a0, e32, m8 vlw.v v0, (a1) sub a0, a0, a4 slli a4, a4, 2 add a1, a1, a4 vlw.v v8, (a2) vfmacc.vf v8, fa0, v0 vsw.v v8, (a2) add a2, a2, a4 bnez a0, saxpy ret
A.6. SGEMM example
# RV64IDV system # # void # sgemm_nn(size_t n, # size_t m, # size_t k, # const float*a, // m * k matrix # size_t lda, # const float*b, // k * n matrix # size_t ldb, # float*c, // m * n matrix # size_t ldc) # # c += a*b (alpha=1, no transpose on input matrices) # matrices stored in C rowmajor order #define n a0 #define m a1 #define k a2 #define ap a3 #define astride a4 #define bp a5 #define bstride a6 #define cp a7 #define cstride t0 #define kt t1 #define nt t2 #define bnp t3 #define cnp t4 #define akp t5 #define bkp s0 #define nvl s1 #define ccp s2 #define amp s3 # Use args as additional temporaries #define ft12 fa0 #define ft13 fa1 #define ft14 fa2 #define ft15 fa3 # This version holds a 16*VLMAX block of C matrix in vector registers # in inner loop, but otherwise does not cache or TLB tiling. sgemm_nn: addi sp, sp, FRAMESIZE sd s0, OFFSET(sp) sd s1, OFFSET(sp) sd s2, OFFSET(sp) # Check for zero size matrices beqz n, exit beqz m, exit beqz k, exit # Convert elements strides to byte strides. ld cstride, OFFSET(sp) # Get arg from stack frame slli astride, astride, 2 slli bstride, bstride, 2 slli cstride, cstride, 2 slti t6, m, 16 bnez t6, end_rows c_row_loop: # Loop across rows of C blocks mv nt, n # Initialize n counter for next row of C blocks mv bnp, bp # Initialize B nloop pointer to start mv cnp, cp # Initialize C nloop pointer c_col_loop: # Loop across one row of C blocks vsetvli nvl, nt, e32 # 32bit vectors, LMUL=1 mv akp, ap # reset pointer into A to beginning mv bkp, bnp # step to next column in B matrix # Initalize current C submatrix block from memory. vlw.v v0, (cnp); add ccp, cnp, cstride; vlw.v v1, (ccp); add ccp, ccp, cstride; vlw.v v2, (ccp); add ccp, ccp, cstride; vlw.v v3, (ccp); add ccp, ccp, cstride; vlw.v v4, (ccp); add ccp, ccp, cstride; vlw.v v5, (ccp); add ccp, ccp, cstride; vlw.v v6, (ccp); add ccp, ccp, cstride; vlw.v v7, (ccp); add ccp, ccp, cstride; vlw.v v8, (ccp); add ccp, ccp, cstride; vlw.v v9, (ccp); add ccp, ccp, cstride; vlw.v v10, (ccp); add ccp, ccp, cstride; vlw.v v11, (ccp); add ccp, ccp, cstride; vlw.v v12, (ccp); add ccp, ccp, cstride; vlw.v v13, (ccp); add ccp, ccp, cstride; vlw.v v14, (ccp); add ccp, ccp, cstride; vlw.v v15, (ccp) mv kt, k # Initialize inner loop counter # Inner loop scheduled assuming 4clock occupancy of vfmacc instruction and singleissue pipeline # Software pipeline loads flw ft0, (akp); add amp, akp, astride; flw ft1, (amp); add amp, amp, astride; flw ft2, (amp); add amp, amp, astride; flw ft3, (amp); add amp, amp, astride; # Get vector from B matrix vlw.v v16, (bkp) # Loop on inner dimension for current C block k_loop: vfmacc.vf v0, ft0, v16 add bkp, bkp, bstride flw ft4, (amp) add amp, amp, astride vfmacc.vf v1, ft1, v16 addi kt, kt, 1 # Decrement k counter flw ft5, (amp) add amp, amp, astride vfmacc.vf v2, ft2, v16 flw ft6, (amp) add amp, amp, astride flw ft7, (amp) vfmacc.vf v3, ft3, v16 add amp, amp, astride flw ft8, (amp) add amp, amp, astride vfmacc.vf v4, ft4, v16 flw ft9, (amp) add amp, amp, astride vfmacc.vf v5, ft5, v16 flw ft10, (amp) add amp, amp, astride vfmacc.vf v6, ft6, v16 flw ft11, (amp) add amp, amp, astride vfmacc.vf v7, ft7, v16 flw ft12, (amp) add amp, amp, astride vfmacc.vf v8, ft8, v16 flw ft13, (amp) add amp, amp, astride vfmacc.vf v9, ft9, v16 flw ft14, (amp) add amp, amp, astride vfmacc.vf v10, ft10, v16 flw ft15, (amp) add amp, amp, astride addi akp, akp, 4 # Move to next column of a vfmacc.vf v11, ft11, v16 beqz kt, 1f # Don't load past end of matrix flw ft0, (akp) add amp, akp, astride 1: vfmacc.vf v12, ft12, v16 beqz kt, 1f flw ft1, (amp) add amp, amp, astride 1: vfmacc.vf v13, ft13, v16 beqz kt, 1f flw ft2, (amp) add amp, amp, astride 1: vfmacc.vf v14, ft14, v16 beqz kt, 1f # Exit out of loop flw ft3, (amp) add amp, amp, astride vfmacc.vf v15, ft15, v16 vlw.v v16, (bkp) # Get next vector from B matrix, overlap loads with jump stalls j k_loop 1: vfmacc.vf v15, ft15, v16 # Save C matrix block back to memory vsw.v v0, (cnp); add ccp, cnp, cstride; vsw.v v1, (ccp); add ccp, ccp, cstride; vsw.v v2, (ccp); add ccp, ccp, cstride; vsw.v v3, (ccp); add ccp, ccp, cstride; vsw.v v4, (ccp); add ccp, ccp, cstride; vsw.v v5, (ccp); add ccp, ccp, cstride; vsw.v v6, (ccp); add ccp, ccp, cstride; vsw.v v7, (ccp); add ccp, ccp, cstride; vsw.v v8, (ccp); add ccp, ccp, cstride; vsw.v v9, (ccp); add ccp, ccp, cstride; vsw.v v10, (ccp); add ccp, ccp, cstride; vsw.v v11, (ccp); add ccp, ccp, cstride; vsw.v v12, (ccp); add ccp, ccp, cstride; vsw.v v13, (ccp); add ccp, ccp, cstride; vsw.v v14, (ccp); add ccp, ccp, cstride; vsw.v v15, (ccp) # Following tail instructions should be scheduled earlier in free slots during C block save. # Leaving here for clarity. # Bump pointers for loop across blocks in one row slli t6, nvl, 2 add cnp, cnp, t6 # Move C block pointer over add bnp, bnp, t6 # Move B block pointer over sub nt, nt, nvl # Decrement element count in n dimension bnez nt, c_col_loop # Any more to do? # Move to next set of rows addi m, m, 16 # Did 16 rows above slli t6, astride, 4 # Multiply astride by 16 add ap, ap, t6 # Move A matrix pointer down 16 rows slli t6, cstride, 4 # Multiply cstride by 16 add cp, cp, t6 # Move C matrix pointer down 16 rows slti t6, m, 16 beqz t6, c_row_loop # Handle end of matrix with fewer than 16 rows. # Can use smaller versions of above decreasing in powersof2 depending on codesize concerns. end_rows: # Not done. exit: ld s0, OFFSET(sp) ld s1, OFFSET(sp) ld s2, OFFSET(sp) addi sp, sp, FRAMESIZE ret
Appendix B: Calling Convention
In the RISCV psABI, the vector registers v0
v31
are all callersaved.
The vstart
, vl
, and vtype
CSRs are also callersaved.
The vxrm
and vxsat
fields have thread storage duration, like the other
fields of the fcsr
.
Executing a system call causes v0
v31
to become unspecified.
Note

This scheme allows system calls that cause context switches to avoid saving and later restoring the vector registers. 
Note

The values that v0 v31 assume after a system call cannot expose
information from other processes, so typically the registers will either
remain intact or will be zeroed.
