RISC-V ISAs provide a set of up to 32×64-bit performance counters and
timers that are accessible via unprivileged XLEN-bit read-only CSR
0xC1F (with the upper 32 bits accessed
via CSR registers
0xC9F on RV32).
These counters are divided between the “Zicntr” and “Zihpm” extensions.
11.1 “Zicntr” Standard Extension for Base Counters and Timers
The Zicntr standard extension comprises the first three of these counters (CYCLE, TIME, and INSTRET), which have dedicated functions (cycle count, real-time clock, and instructions retired, respectively). The Zicntr extension depends on the Zicsr extension.
RV32I provides a number of 64-bit read-only user-level counters, which
are mapped into the 12-bit CSR address space and accessed in 32-bit
pieces using CSRRS instructions. In RV64I, the CSR instructions can
manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and
RDINSTRET pseudoinstructions read the full 64 bits of the
instret counters. Hence, the RDCYCLEH, RDTIMEH,
and RDINSTRETH instructions are RV32I-only.
The RDCYCLE pseudoinstruction reads the low XLEN bits of the
cycle CSR which holds a count of the number of clock cycles
executed by the processor core on which the hart is running from an
arbitrary start time in the past. RDCYCLEH is an RV32I-only
instruction that reads bits 63–32 of the same cycle counter. The
underlying 64-bit counter should never overflow in practice. The rate
at which the cycle counter advances will depend on the implementation
and operating environment. The execution environment should provide a
means to determine the current rate (cycles/second) at which the cycle
counter is incrementing.
The RDTIME pseudoinstruction reads the low XLEN bits of the
time CSR, which counts wall-clock real time that has passed from an
arbitrary start time in the past.
RDTIMEH is an RV32I-only instruction that reads bits 63–32 of the same
The underlying 64-bit counter increments by one with each tick of the
real-time clock, and, for realistic real-time clock frequencies, should never
overflow in practice.
The execution environment should provide a means of determining the period of
a counter tick (seconds/tick).
The period must be constant.
The real-time clocks of all harts in a single user application
should be synchronized to within one tick of the real-time clock.
The environment should provide a means to determine the accuracy of the clock
(i.e., the maximum relative error between the nominal and actual real-time
The RDINSTRET pseudoinstruction reads the low XLEN bits of the
instret CSR, which counts the number of instructions retired by
this hart from some arbitrary start point in the past. RDINSTRETH is
an RV32I-only instruction that reads bits 63–32 of the same
instruction counter. The underlying 64-bit counter should never
overflow in practice.
The following code sequence will read a valid 64-bit cycle counter value into
x2, even if the counter overflows its lower half between reading its upper
and lower halves.
11.2 “Zihpm” Standard Extension for Hardware Performance Counters
The Zihpm extension comprises the 29 additional unprivileged 64-bit
hardware performance counters,
For RV32, the upper 32 bits of these performance counters are
accessible via additional CSRs
hpmcounter31h. These counters count platform-specific events and
are configured via additional privileged registers. The number and
width of these additional counters, and the set of events they count,
The Zihpm extension depends on the Zicsr extension.