Colophon
This document is released under the Creative Commons Attribution 4.0 International License.
It describes the BitManip Zba, Zbb, Zbc and Zbs extensions being submitted for public review.
Acknowledgments
Contributors to this specification (in alphabetical order) include:
Jacob Bachmeyer,
Allen Baum,
Ari Ben,
Alex Bradbury,
Steven Braeger,
Rogier Brussee,
Michael Clark,
Ken Dockser,
Paul Donahue,
Dennis Ferguson,
Fabian Giesen,
John Hauser,
Robert Henry,
Bruce Hoult,
Powei Huang,
Ben Marshall,
Rex McCrary,
Lee Moore,
Jiří Moravec,
Samuel Neves,
Markus Oberhumer,
Christopher Olson,
Nils Pipenbrinck,
Joseph Rahmeh,
Xue Saw,
Tommy Thorn,
Philipp Tomsich,
Avishai Tvila,
Andrew Waterman,
Thomas Wicki, and
Claire Wolf.
We express our gratitude to everyone that contributed to, reviewed or improved this specification through their comments and questions.
Bitmanipulation a, b, c and s extensions grouped for public review and ratification
The bitmanipulation (bitmanip) extension collection is comprised of several component extensions to the base RISCV architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided, rather than one large extension. Each of these smaller extensions is grouped by common function and use case, and each of which has its own Zb*extension name.
Each bitmanip extension includes a group of several bitmanip instructions that have similar purposes and that can often share the same logic. Some instructions are available in only one extension while others are available in several. The instructions have mnemonics and encodings that are independent of the extensions in which they appear. Thus, when implementing extensions with overlapping instructions, there is no redundancy is logic or encoding.
The bitmanip extensions are defined for RV32 and RV64. Most of the instructions are expected to be forward compatible with RV128. While the shiftimmediate instructions are defined to have at most a 6bit immediate field, a 7th bit is available in the encoding space should this be needed for RV128.
Word Instructions
The bitmanip extension follows the convention in RV64 that wsuffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the leastsignificant 32bits as signed values and produce a 32bit signed result that is signextended to XLEN.
Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32bit value that is extracted from the least significant 32 bits of the specified register. Other than that, these perform full XLEN operations.
Bitmanip instructions with the suffix .b, .h and .w only look at the least significant 8bits, 16bits and 32bits of the input (respectively) and produce an XLENwide result that is signextended or zeroextended, based on specific instruction.
Pseudocode for instruction semantics
The semantics of each instruction in Instructions (in alphabetical order) is expressed in a SAILlike syntax.
1. Extensions
The first group of bitmanip extensions to be release for Public Review are:
Below is a list of all of the instructions (and pseudoinstructions) that are included in these extensions along with their specific mapping:
RV32  RV64  Mnemonic  Instruction  Zba  Zbb  Zbc  Zbs 

X 
add.uw rd, rs1, rs2 
X 

X 
X 
andn rd, rs1, rs2 
X 

X 
X 
clmul rd, rs1, rs2 
X 

X 
X 
clmulh rd, rs1, rs2 
X 

X 
X 
clmulr rd, rs1, rs2 
X 

X 
X 
clz rd, rs 
X 

X 
clzw rd, rs 
X 

X 
X 
cpop rd, rs 
X 

X 
cpopw rd, rs 
X 

X 
X 
ctz rd, rs 
X 

X 
ctzw rd, rs 
X 

X 
X 
max rd, rs1, rs2 
X 

X 
X 
maxu rd, rs1, rs2 
X 

X 
X 
min rd, rs1, rs2 
X 

X 
X 
minu rd, rs1, rs2 
X 

X 
X 
orc.b rd, rs1, rs2 
X 

X 
X 
orn rd, rs1, rs2 
X 

X 
X 
rev8_rd_, rs 
X 

X 
X 
rol rd, rs1, rs2 
X 

X 
rolw rd, rs1, rs2 
X 

X 
X 
ror rd, rs1, rs2 
X 

X 
X 
rori rd, rs1, shamt 
X 

X 
roriw rd, rs1, shamt 
X 

X 
rorw rd, rs1, rs2 
X 

X 
X 
bclr rd, rs1, rs2 
X 

X 
X 
bclri rd, rs1, imm 
X 

X 
X 
bext rd, rs1, rs2 
X 

X 
X 
bexti rd, rs1, imm 
X 

X 
X 
binv rd, rs1, rs2 
X 

X 
X 
binvi rd, rs1, imm 
X 

X 
X 
bset rd, rs1, rs2 
X 

X 
X 
bseti rd, rs1, imm 
X 

X 
X 
sext.b rd, rs 
X 

X 
X 
sext.h rd, rs 
X 

X 
X 
sh1add rd, rs1, rs2 
X 

X 
sh1add.uw rd, rs1, rs2 
X 

X 
X 
sh2add rd, rs1, rs2 
X 

X 
sh2add.uw rd, rs1, rs2 
X 

X 
X 
sh3add rd, rs2, rs2 
X 

X 
sh3add.uw rd, rs1, rs2 
X 

X 
slli.uw rd, rs1, imm 
X 

X 
X 
xnor rd, rs1, rs2 
X 

X 
X 
zext.h rd, rs 
X 
1.1. Zba extension
The Zba extension is frozen. 
The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned wordsized and XLENsized indices: a shifted index is added to a base address.
The shift and add instructions to a left shift of 1, 2, or 3 because these are commonly found in realworld code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations.
While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw — added in this sub extension — can be used when the index is to be interpreted as an unsigned word.
The following instructions comprise the Zba extension:
RV32  RV64  Mnemonic  Instruction 

✓ 
add.uw rd, rs1, rs2 

✓ 
✓ 
sh1add rd, rs1, rs2 

✓ 
sh1add.uw rd, rs1, rs2 

✓ 
✓ 
sh2add rd, rs1, rs2 

✓ 
sh2add.uw rd, rs1, rs2 

✓ 
✓ 
sh3add rd, rs2, rs2 

✓ 
sh3add.uw rd, rs1, rs2 

✓ 
slli.uw rd, rs1, imm 
1.2. Zbb: Basic bitmanipulation
The Zbb extension is frozen. 
1.2.1. Logical with negate
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
andn rd, rs1, rs2 

✓ 
✓ 
orn rd, rs1, rs2 

✓ 
✓ 
xnor rd, rs1, rs2 
Implementation Hint
The Logical with Negate instructions can be implemented by inverting the rs2 inputs to the baserequired AND, OR, and XOR logic instructions. In some implementations, the inverter on rs2 used for subtraction can be reused for this purpose. 
1.2.2. Count leading/training zero bits
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
clz rd, rs 

✓ 
clzw rd, rs 

✓ 
✓ 
ctz rd, rs 

✓ 
ctzw rd, rs 
1.2.3. Count population
These instructions count the number of set bits (1bits). This is also commonly referred to as population count.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
cpop rd, rs 

✓ 
cpopw rd, rs 
1.2.4. Integer minimum/maximum
The integer minimum/maximum instructions are arithmetic Rtype instructions that returns the smaller/larger of two operands.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
max rd, rs1, rs2 

✓ 
✓ 
maxu rd, rs1, rs2 

✓ 
✓ 
min rd, rs1, rs2 

✓ 
✓ 
minu rd, rs1, rs2 
1.2.5. Sign and zeroextension
These instructions perform the signextension or zeroextension of the least significant 8 bits, 16 bits or 32 bits of the source register.
These instructions replace the generalized idioms slli rD,rS,(XLEN<size>) + srli
(for zeroextension) or slli + srai
(for signextension) for the signextension of 8bit and 16bit quantities, and for the zeroextension of 16bit and 32bit quantities.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
sext.b rd, rs 

✓ 
✓ 
sext.h rd, rs 

✓ 
✓ 
zext.h rd, rs 
1.3. Bitwise rotation
Bitwise rotation instructions are similar to the shiftlogical operations from the base spec. However, where the shiftlogical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value. Such operations are also referred to as ‘circular shifts’.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
rol rd, rs1, rs2 

✓ 
rolw rd, rs1, rs2 

✓ 
✓ 
ror rd, rs1, rs2 

✓ 
✓ 
rori rd, rs1, shamt 

✓ 
roriw rd, rs1, shamt 

✓ 
rorw rd, rs1, rs2 
Architecture Explanation
The rotate instructions were included to replace a common fourinstruction sequence to achieve the same effect (neg; sll/srl; srl/sll; or) 
1.3.1. OR Combine
orc.b sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.
The intended usecase are stringprocessing functions, like strlen and strcpy, which can utilize orc.b for testing for zero bytes, and counting trailing nonzero bytes in a word.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
orc.b rd, rs 
1.3.2. Bytereverse
This instruction reverses the byteordering in a register.
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
rev8 rd, rs 
1.4. Zbc: Carryless multiplication
The Zbc extension is frozen. 
Carryless multiplication is the multiplication in the polynomial ring over GF(2).
clmul produces the lower half of the carryless product and clmulh produces the upper half of the 2✕XLEN carryless product.
clmulr produces bits 2✕XLEN−2:XLEN1 of the 2✕XLEN carryless product. That means clmulh is equivalent to clmulr followed by a 1bit right shift. (The MSB of a clmulh result is always zero.)
RV32  RV64  Mnemonic  Instruction 

✓ 
✓ 
clmul rd, rs1, rs2 

✓ 
✓ 
clmulh rd, rs1, rs2 

✓ 
✓ 
clmulr rd, rs1, rs2 
1.5. Zbs: Singlebit instructions
The Zbs extension is frozen. 
The singlebit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index.
RV32  RV64  Mnemonic  Instruction 

X 
X 
bclr rd, rs1, rs2 

X 
X 
bclri rd, rs1, imm 

X 
X 
bext rd, rs1, rs2 

X 
X 
bexti rd, rs1, imm 

X 
X 
binv rd, rs1, rs2 

X 
X 
binvi rd, rs1, imm 

X 
X 
bset rd, rs1, rs2 

X 
X 
bseti rd, rs1, imm 
2. Instructions (in alphabetical order)
2.1. add.uw
 Synopsis

Add unsigned word
 Mnemonic

add.uw rd, rs1, rs2
 Pseudoinstructions

zext.w rd, rs1 → add.uw rd, rs1, zero
 Encoding
 Description

This instruction performs an XLENwide addition between rs2 and the zeroextended leastsignificant word of rs1.
 Operation
let base = X(rs2);
let index = EXTZ(X(rs1)[31..0]);
X(rd) = base + index;
 Included in
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2.2. andn
 Synopsis

AND with inverted operand
 Mnemonic

andn rd, rs1, rs2
 Encoding
 Description

This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.
 Operation
X(rd) = X(rs1) & ~X(rs2);
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
0.93 
Frozen 
2.3. bclr
 Synopsis

SingleBit Clear (Register)
 Mnemonic

bclr rd, rs1, rs2
 Encoding
 Description

This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.
 Operation
let index = X(rs2) & (XLEN  1);
X(rd) = X(rs1) & ~(1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
Frozen 
2.4. bclri
 Synopsis

SingleBit Clear (Immediate)
 Mnemonic

bclri rd, rs1, shamt
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction returns rs1 with a single bit cleared at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 Operation
let index = shamt & (XLEN  1);
X(rd) = X(rs1) & ~(1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
Frozen 
2.5. bext
 Synopsis

SingleBit Extract (Register)
 Mnemonic

bext rd, rs1, rs2
 Encoding
 Description

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.
 Operation
let index = X(rs2) & (XLEN  1);
X(rd) = (X(rs1) >> index) & 1;
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
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2.6. bexti
 Synopsis

SingleBit Extract (Immediate)
 Mnemonic

bexti rd, rs1, shamt
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 Operation
let index = shamt & (XLEN  1);
X(rd) = (X(rs1) >> index) & 1;
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
Frozen 
2.7. binv
 Synopsis

SingleBit Invert (Register)
 Mnemonic

binv rd, rs1, rs2
 Encoding
 Description

This instruction returns rs1 with a single bit inverted at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.
 Operation
let index = X(rs2) & (XLEN  1);
X(rd) = X(rs1) ^ (1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
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2.8. binvi
 Synopsis

SingleBit Invert (Immediate)
 Mnemonic

binvi rd, rs1, shamt
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 Operation
let index = shamt & (XLEN  1);
X(rd) = X(rs1) ^ (1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
Frozen 
2.9. bset
 Synopsis

SingleBit Set (Register)
 Mnemonic

bset rd, rs1,rs2
 Encoding
 Description

This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.
 Operation
let index = X(rs2) & (XLEN  1);
X(rd) = X(rs1)  (1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
Frozen 
2.10. bseti
 Synopsis

SingleBit Set (Immediate)
 Mnemonic

bseti rd, rs1,shamt
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 Operation
let index = shamt & (XLEN  1);
X(rd) = X(rs1)  (1 << index)
 Included in
Extension  Minimum version  Lifecycle state 

Zbs (Singlebit instructions) 
0.93 
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2.11. clmul
 Synopsis

Carryless multiply (lowpart)
 Mnemonic

clmul rd, rs1, rs2
 Encoding
 Description

clmul produces the lower half of the 2·XLEN carryless product.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let output : xlenbits = 0;
foreach (i from 0 to xlen by 1) {
output = if ((rs2_val >> i) & 1)
then output ^ (rs1_val << i);
else output;
}
X[rd] = output
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2.12. clmulh
 Synopsis

Carryless multiply (highpart)
 Mnemonic

clmulh rd, rs1, rs2
 Encoding
 Description

clmulh produces the upper half of the 2·XLEN carryless product.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let output : xlenbits = 0;
foreach (i from 1 to xlen by 1) {
output = if ((rs2_val >> i) & 1)
then output ^ (rs1_val >> (xlen  i));
else output;
}
X[rd] = output
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2.13. clmulr
 Synopsis

Carryless multiply (reversed)
 Mnemonic

clmulr rd, rs1, rs2
 Encoding
 Description

clmulr produces bits 2·XLEN−2:XLEN1 of the 2·XLEN carryless product.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let output : xlenbits = 0;
foreach (i from 0 to (xlen  1) by 1) {
output = if ((rs2_val >> i) & 1)
then output ^ (rs1_val >> (xlen  i  1));
else output;
}
X[rd] = output
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2.14. clz
 Synopsis

Count leading zero bits
 Mnemonic

clz rd, rs
 Encoding
 Description

This instruction counts the number of 0’s before the first 1, starting at the mostsignificant bit (i.e., XLEN1) and progressing to bit 0. Accordingly, if the input is 0, the output is XLEN, and if the mostsignificant bit of the input is a 1, the output is 0.
 Operation
val HighestSetBit : forall ('N : Int), 'N >= 0. bits('N) > int
function HighestSetBit x = {
foreach (i from (xlen  1) to 0 by 1 in dec)
if [x[i]] == 0b1 then return(i) else ();
return 1;
}
let rs = X(rs);
X[rd] = (xlen  1)  HighestSetBit(rs);
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
0.93 
Frozen 
2.15. clzw
 Synopsis

Count leading zero bits in word
 Mnemonic

clzw rd, rs
 Encoding
 Description

This instruction counts the number of 0’s before the first 1 starting at bit 31 and progressing to bit 0. Accordingly, if the leastsignificant word is 0, the output is 32, and if the mostsignificant bit of the word (i.e., bit 31) is a 1, the output is 0.
 Operation
val HighestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) > int
function HighestSetBit32 x = {
foreach (i from 31 to 0 by 1 in dec)
if [x[i]] == 0b1 then return(i) else ();
return 1;
}
let rs = X(rs);
X[rd] = 31  HighestSetBit(rs);
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
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2.16. cpop
 Synopsis

Count set bits
 Mnemonic

cpop rd, rs
 Encoding
 Description

This instructions counts the number of 1’s (i.e., set bits) in the source register.
 Operation
let bitcount = 0;
let rs = X(rs);
foreach (i from 0 to (xlen  1) in inc)
if rs[i] == 0b1 then bitcount = bitcount + 1 else ();
X[rd] = bitcount
Software Hint
This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight. The GCC builtin function 
 Included in
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Zbb (Basic bitmanipulation) 
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2.17. cpopw
 Synopsis

Count set bits in word
 Mnemonic

cpopw rd, rs
 Encoding
 Description

This instructions counts the number of 1’s (i.e., set bits) in the leastsignificant word of the source register.
 Operation
let bitcount = 0;
let val = X(rs);
foreach (i from 0 to 31 in inc)
if val[i] == 0b1 then bitcount = bitcount + 1 else ();
X[rd] = bitcount
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
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2.18. ctz
 Synopsis

Count trailing zeros
 Mnemonic

ctz rd, rs
 Encoding
 Description

This instruction counts the number of 0’s before the first 1, starting at the leastsignificant bit (i.e., 0) and progressing to the mostsignificant bit (i.e., XLEN1). Accordingly, if the input is 0, the output is XLEN, and if the leastsignificant bit of the input is a 1, the output is 0.
 Operation
val LowestSetBit : forall ('N : Int), 'N >= 0. bits('N) > int
function LowestSetBit x = {
foreach (i from 0 to (xlen  1) by 1 in dec)
if [x[i]] == 0b1 then return(i) else ();
return xlen;
}
let rs = X(rs);
X[rd] = LowestSetBit(rs);
 Included in
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Zbb (Basic bitmanipulation) 
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2.19. ctzw
 Synopsis

Count trailing zero bits in word
 Mnemonic

ctzw rd, rs
 Encoding
 Description

This instruction counts the number of 0’s before the first 1, starting at the leastsignificant bit (i.e., 0) and progressing to the mostsignificant bit of the leastsignificant word (i.e., 31). Accordingly, if the leastsignificant word is 0, the output is 32, and if the leastsignificant bit of the input is a 1, the output is 0.
 Operation
val LowestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) > int
function LowestSetBit32 x = {
foreach (i from 0 to 31 by 1 in dec)
if [x[i]] == 0b1 then return(i) else ();
return 32;
}
let rs = X(rs);
X[rd] = LowestSetBit32(rs);
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
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2.20. max
 Synopsis

Maximum
 Mnemonic

max rd, rs1, rs2
 Encoding
 Description

This instruction returns the larger of two signed integers.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result = if rs1_val <_s rs2_val
then rs2_val
else rs1_val;
X(rd) = result;
Software Hint
Calculating the absolute value of a signed integer can be performed using the following sequence: neg rD,rS followed by max rD,rS,rD. When using this common sequence, it is suggested that they are scheduled with no intervening instructions so that implementations that are so optimized can fuse them together. 
 Included in
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Zbb (Basic bitmanipulation) 
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2.21. maxu
 Synopsis

Unsigned maximum
 Mnemonic

maxu rd, rs1, rs2
 Encoding
 Description

This instruction returns the larger of two unsigned integers.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result = if rs1_val <_u rs2_val
then rs2_val
else rs1_val;
X(rd) = result;
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
0.93 
Frozen 
2.22. min
 Synopsis

Minimum
 Mnemonic

min rd, rs1, rs2
 Encoding
 Description

This instruction returns the smaller of two signed integers.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result = if rs1_val <_s rs2_val
then rs1_val
else rs2_val;
X(rd) = result;
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
0.93 
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2.23. minu
 Synopsis

Unsigned minimum
 Mnemonic

minu rd, rs1, rs2
 Encoding
 Description

This instruction returns the smaller of two unsigned integers.
 Operation
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result = if rs1_val <_u rs2_val
then rs1_val
else rs2_val;
X(rd) = result;
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
0.93 
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2.24. orc.b
 Synopsis

Bitwise ORCombine, byte granule
 Mnemonic

orc.b rd, rs
 Encoding
 Description

Combines the bits within every byte through a reciprocal bitwise logical OR. This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.
 Operation
let input = X(rs);
let output : xlenbits = 0;
let j = xlen;
foreach (i from 0 to xlen by 8) {
output[(i + 7)..i] = if input[(i  7)..i] == 0
then 0b00000000
else 0b11111111;
}
X[rd] = output;
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
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2.25. orn
 Synopsis

OR with inverted operand
 Mnemonic

orn rd, rs1, rs2
 Encoding
 Description

This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.
 Operation
X(rd) = X(rs1)  ~X(rs2);
 Included in
Extension  Minimum version  Lifecycle state 

Zbb (Basic bitmanipulation) 
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2.26. rev8
 Synopsis

Bytereverse register
 Mnemonic

rev8 rd, rs
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction reverses the order of the bytes in a register.
 Operation
let input = X(rs);
let output : xlenbits = 0;
let j = xlen;
foreach (i from 0 to xlen by 8) {
output[i..(i + 7)] = input[(j  7)..j];
j = j  8;
}
X[rd] = output
Note
The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64. 
Software Hint
The bytereverse operation is only available for the full register
width. To emulate wordsized and halfwordsized bytereversal,
perform a 
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2.27. rol
 Synopsis

Rotate Left (Register)
 Mnemonic

rol rd, rs1, rs2
 Encoding
 Description

This instruction performs a rotate left of rs1 by the amount in leastsignificant log2(XLEN) bits of rs2.
 Operation
let shamt = if xlen == 32
then X(rs2)[4..0]
else X(rs2)[5..0];
let result = (X(rs1) << shamt)  (X(rs2) >> (xlen  shamt));
X(rd) = result;
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2.28. rolw
 Synopsis

Rotate Left Word (Register)
 Mnemonic

rolw rd, rs1, rs2
 Encoding
 Description

This instruction performs a rotate left on the leastsignificant word of rs1 by the amount in leastsignificant 5 bits of rs2. The resulting word value is signextended by copying bit 31 to all of the moresignificant bits.
 Operation
let rs1 = EXTZ(X(rs1)[31..0])
let shamt = X(rs2)[4..0];
let result = (rs1 << shamt)  (rs1 >> (32  shamt));
X(rd) = EXTS(result);
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2.29. ror
 Synopsis

Rotate Right
 Mnemonic

ror rd, rs1, rs2
 Encoding
 Description

This instruction performs a rotate right of rs1 by the amount in leastsignificant log2(XLEN) bits of rs2.
 Operation
let shamt = if xlen == 32
then X(rs2)[4..0]
else X(rs2)[5..0];
let result = (X(rs1) >> shamt)  (X(rs2) << (xlen  shamt));
X(rd) = result;
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2.30. rori
 Synopsis

Rotate Right (Immediate)
 Mnemonic

rori rd, rs1, shamt
 Encoding (RV32)
 Encoding (RV64)
 Description

This instruction performs a rotate right of rs1 by the amount in the leastsignificant log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 Operation
let shamt = if xlen == 32
then shamt[4..0]
else shamt[5..0];
let result = (X(rs1) >> shamt)  (X(rs2) << (xlen  shamt));
X(rd) = result;
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2.31. roriw
 Synopsis

Rotate Right Word by Immediate
 Mnemonic

roriw rd, rs1, shamt
 Encoding
 Description

This instruction performs a rotate right on the leastsignificant word of rs1 by the amount in the leastsignificant log2(XLEN) bits of shamt. The resulting word value is signextended by copying bit 31 to all of the moresignificant bits.
 Operation
let rs1 = EXTZ(X(rs1)[31..0];
let result = (rs1 >> shamt[4..0])  (X(rs1) << (32  shamt[4..0]));
X(rd) = EXTS(result[31..0]);
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2.32. rorw
 Synopsis

Rotate Right Word (Register)
 Mnemonic

rorw rd, rs1, rs2
 Encoding
 Description

This instruction performs a rotate right on the leastsignificant word of rs1 by the amount in leastsignificant 5 bits of rs2. The resultant word is signextended by copying bit 31 to all of the moresignificant bits.
 Operation
let rs1 = EXTZ(X(rs1)[31..0])
let shamt = X(rs2)[4..0];
let result = (rs1 >> shamt)  (rs1 << (32  shamt));
X(rd) = EXTS(result);
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2.33. sext.b
 Synopsis

Signextend byte
 Mnemonic

sext.b rd, rs
 Encoding
 Description

This instruction signextends the leastsignificant byte in the source to XLEN by copying the mostsignificant bit in the byte (i.e., bit 7) to all of the moresignificant bits.
 Operation
X(rd) = EXTS(X(rs)[7..0]);
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2.34. sext.h
 Synopsis

Signextend halfword
 Mnemonic

sext.h rd, rs
 Encoding
 Description

This instruction signextends the leastsignificant halfword in rs to XLEN by copying the mostsignificant bit in the halfword (i.e., bit 15) to all of the moresignificant bits.
 Operation
X(rd) = EXTS(X(rs)[15..0]);
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2.35. sh1add
 Synopsis

Shift left by 1 and add
 Mnemonic

sh1add rd, rs1, rs2
 Encoding
 Description

This instruction shifts rs1 to the left by 1 bit and adds it to rs2.
 Operation
X(rd) = X(rs2) + (X(rs1) << 1);
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2.36. sh1add.uw
 Synopsis

Shift unsigned word left by 1 and add
 Mnemonic

sh1add.uw rd, rs1, rs2
 Encoding
 Description

This instruction performs an XLENwide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the leastsignificant word of rs1 and shifting it left by 1 place.
 Operation
let base = X(rs2);
let index = EXTZ(X(rs1)[31..0]);
X(rd) = base + (index << 1);
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2.37. sh2add
 Synopsis

Shift left by 2 and add
 Mnemonic

sh2add rd, rs1, rs2
 Encoding
 Description

This instruction shifts rs1 to the left by 2 places and adds it to rs2.
 Operation
X(rd) = X(rs2) + (X(rs1) << 2);
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2.38. sh2add.uw
 Synopsis

Shift unsigned word left by 2 and add
 Mnemonic

sh2add.uw rd, rs1, rs2
 Encoding
 Description

This instruction performs an XLENwide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the leastsignificant word of rs1 and shifting it left by 2 places.
 Operation
let base = X(rs2);
let index = EXTZ(X(rs1)[31..0]);
X(rd) = base + (index << 2);
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2.39. sh3add
 Synopsis

Shift left by 3 and add
 Mnemonic

sh3add rd, rs1, rs2
 Encoding
 Description

This instruction shifts rs1 to the left by 3 places and adds it to rs2.
 Operation
X(rd) = X(rs2) + (X(rs1) << 3);
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2.40. sh3add.uw
 Synopsis

Shift unsigned word left by 3 and add
 Mnemonic

sh3add.uw rd, rs1, rs2
 Encoding
 Description

This instruction performs an XLENwide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the leastsignificant word of rs1 and shifting it left by 3 places.
 Operation
let base = X(rs2);
let index = EXTZ(X(rs1)[31..0]);
X(rd) = base + (index << 3);
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2.41. slli.uw
 Synopsis

Shiftleft unsigned word (Immediate)
 Mnemonic

slli.uw rd, rs1, shamt
 Encoding
 Description

This instruction takes the leastsignificant word of rs1, zeroextends it, and shifts it left by the immediate.
 Operation
X(rd) = (EXTZ(X(rs)[31..0]) << shamt);
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Architecture Explanation
This instruction is the same as slli with zext.w performed on rs1 before shifting. 
2.42. xnor
 Synopsis

Exclusive NOR
 Mnemonic

xnor rd, rs1, rs2
 Encoding