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Base ISA Variants

Base ISA misa GCC Macro
rv32e Reduced version of the 32 bit integer ISA designed for embedded systems 0x00000010 (bit 4) __riscv __riscv_32e __riscv_xlen=32
rv32i A 32 bit integer ISA sufficient to form a compiler target and to support modern operating system environment 0x00000100 (bit 8) __riscv __riscv_xlen=32
rv64i A 64 bit integer ISA sufficient to form a compiler target and to support modern operating system environment 0x00000100 (bit 8) __riscv __riscv_xlen=64
rv128 A variant of the RISC-V ISA supporting a flat 128-bit address space 0x00000100 (bit 8)

ISA Extensions

Extension misa GCC Macro Version
M Integer Multiply/Divide extension 0x00001000 (bit 12) __riscv_mul __riscv_div __riscv_muldiv 2.0 ratification
A Atomic extension 0x00000001 (bit 0) __riscv_atomic 2.0 frozen
F Single-precision floating-point extension 0x00000020 (bit 5) __riscv_fdiv __riscv_float_abi_single __riscv_flen=32 2.2 ratification
D Double-precision floating-point extension 0x00000008 (bit 3) __riscv_fdiv __riscv_float_abi_double __riscv_flen=64 2.2 ratification
Q Quad-precision floating-point extension 0x00010000 (bit 16) 2.2 ratification
C Compressed extension 0x00000004 (bit 2) __riscv_compressed 2.0 ratification
L Decimal Floating-Point extension 0x00000800 (bit 11)
B Bit-Manipulation extension 0x00000002 (bit 1) 0.0 draft
J Dynamically Translated Languages extension 0x00000200 (bit 9)
T Transactional Memory extension 0x00200000 (bit 21)
P Packed-SIMD extension 0x00008000 (bit 15) 0.2 draft
V Vector extension 0x00200000 (bit 21) 0.7 draft
N User-level interrupts supported 0x00002000 (bit 13) 1.1 draft
Counters Performance Counter CSRs 2.0 draft
G Additional standard extensions present 0x00000040 (bit 6)
H Hypervisor extension 0x00000080 (bit 7)
X Non-standard extensions present 0x00800000 (bit 23)
Zam Standard Extension for Misaligned Atomics 0.1 draft
Zicsr Control and Status Register (CSR) Instructions 2.0 ratification
Zifencei Instruction-Fetch Fence 2.0 ratification
Ztso Standard Extension for Total Store Ordering 0.1 frozen

Priviledge Levels

Mode misa
m machine
s supervisor 0x00040000 (bit 18)
u user 0x00100000 (bit 20)