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Base ISA Variants ISA Extensions Priviledge Levels

Base ISA Variants

Base ISA Description misa GCC Support GCC Macro
rv32e Reduced version of the 32 bit integer ISA designed for embedded systems Bit: 4, 0x00000010 Yes, 8.1.0 __riscv __riscv_32e __riscv_xlen=32
rv32i A 32 bit integer ISA sufficient to form a compiler target and to support modern operating system environment Bit: 8, 0x00000100 Yes, 7.2.0 __riscv __riscv_xlen=32
rv64i A 64 bit integer ISA sufficient to form a compiler target and to support modern operating system environment Bit: 8, 0x00000100 Yes, 7.2.0 __riscv __riscv_xlen=64
rv128 A variant of the RISC-V ISA supporting a flat 128-bit address space Bit: 8, 0x00000100 No

ISA Extensions

ID Extension misa Spec Version GCC Support GCC Macro
M Integer Multiply/Divide extension Bit: 12, 0x00001000 2.0 ratification Yes, from 7.2.0. __riscv_mul __riscv_div __riscv_muldiv
A Atomic extension Bit: 0, 0x00000001 2.0 frozen Yes, from 7.2.0. __riscv_atomic
F Single-precision floating-point extension Bit: 5, 0x00000020 2.2 ratification Yes, from 7.2.0. __riscv_fdiv __riscv_float_abi_single __riscv_flen=32
D Double-precision floating-point extension Bit: 3, 0x00000008 2.2 ratification Yes, from 7.2.0. __riscv_fdiv __riscv_float_abi_double __riscv_flen=64
Q Quad-precision floating-point extension Bit: 16, 0x00010000 2.2 ratification No
C Compressed extension Bit: 2, 0x00000004 2.0 ratification Yes, from 7.2.0. __riscv_compressed
L Decimal Floating-Point extension Bit: 11, 0x00000800 No
B Bit-Manipulation extension Bit: 1, 0x00000002 0.0 draft In development (riscv-bitmanip).
J Dynamically Translated Languages extension Bit: 9, 0x00000200 No
T Transactional Memory extension Bit: 21, 0x00200000 No
P Packed-SIMD extension Bit: 15, 0x00008000 0.2 draft No
V Vector extension Bit: 21, 0x00200000 0.7 draft In development (9.2.0-rvv). __riscv_vector
N User-level interrupts supported Bit: 13, 0x00002000 1.1 draft No
Counters Performance Counter CSRs 2.0 draft No
G Additional standard extensions present Bit: 6, 0x00000040 No
H Hypervisor extension Bit: 7, 0x00000080 No
X Non-standard extensions present Bit: 23, 0x00800000 No
Zam Standard Extension for Misaligned Atomics 0.1 draft No
Zicsr Control and Status Register (CSR) Instructions 2.0 ratification No
Zifencei Instruction-Fetch Fence 2.0 ratification No
Ztso Standard Extension for Total Store Ordering 0.1 frozen No

Priviledge Levels

ID Mode misa
m machine
s supervisor Bit: 18, 0x00040000
u user Bit: 20, 0x00100000
d debug

References