A blog about embedded development for the RISC-V ISA. General information on the RISC-V ISA.
A few years ago I was responsible for the bring up of some deep embedded firmware applications and RTOSs on an in-house developed RISC-V core. As RISC-V was a new architecture, there was not much public information available to help in that task. At that time I decided to put back the knowledge gained about RISC-V to the community.
The contents here are anything I’d like to reference during development. Things that as a developer of RISC-V embedded software I found interesting. The initial focus is on low level/bare metal development.
RISC-V is a constantly changing specification. This blog and site can get out of date quickly - for that reason I’ve tried to always reference original material. However, the RISC-V specifications are often written for hardware architects and those interested in specific applications - the purpose of this blog is to capture information useful to a low level software author.
What is RISC-V
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
For embedded development RISC-V is now an alternative to ARM-Cortex M, although it won’t displace ARM anytime soon. It’s also an alternative to royalty free legacy cores, such as synthesizable 8051 cores, that remain in many deeply embedded applications.
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The banner image at the top is a Commodore-PET from the akihabara junk street, admittedly unrelated to RISC-V or embedded programming.