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Baremetal Vectored Interrupts in C for RISC-V

September 25, 2021|Code (toolchain,baremetal,C)

An example of using vectored interrupts in C.

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Baremetal Timer Driver in C for RISC-V

September 24, 2021|Code (toolchain,baremetal,C)

An example of a timer driver in C has been added.

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Baremetal Startup in C for RISC-V

September 24, 2021|Code (toolchain,baremetal,C)

An example of a startup code in C.

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Machine Readable Specification Data

September 10, 2021|Toolchain (registers,spec,interrupts,opcodes)

As RISC-V is a new architecture so there will be new development at all layers of the software and hardware stack. Rather than write code based on human language specifications from scratch, a smarter way to work can be to translate a machine readable specification to code.

“Machine Readable” does not need to be an all encompassing formal model of the architecture, there are many convenient formats such as csv, yaml, xml and json that can be parsed and transformed using the packages available in most scripting languages.

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Baremetal Timer Driver in C++ for RISC-V

August 13, 2021|Code (toolchain,baremetal,C++)

An example of a timer driver.

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Baremetal Interrupt in C++ for RISC-V

August 13, 2021|Code (toolchain,baremetal,C++)

An example of using interrupts.

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Baremetal Startup Code in C++ for RISC-V

April 13, 2021|Code (toolchain,baremetal,C++)

An example of baremetal bootstrap code for RISC-V in C++.

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CMake Cross Compilation for RISC-V Targets

March 20, 2021|Toolchain (toolchain,baremetal)

An example of cross compiling a baremetal program to RISC-V with CMake.

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RISC-V Compile Targets, GCC

February 09, 2021|Toolchain (gcc,base_isa,extensions,abi)

Note to self: When compiling the riscv-toolchain for embedded systems, set the configure options!

The toolchain can be cloned from the RISC-V official github. Once the dependencies are installed it’s straight forward to compile.

$ git clone --recursive  https://github.com/riscv/riscv-gnu-toolchain.git

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RISC-V CSR Access

November 18, 2020|Code (registers,code,baremetal,quickref)

For baremetal programming I’ll often need to access CSRs, e.g. mstatus.mie for critical sections, mcause in interrupts handlers, etc. Defining function wrappers for accessing these registers creates easier to understand code, however writing these wrappers is pretty tedious.

The quick reference on this blog is generated from a YAML description (csr.yaml). Using that with a web template engine script (generators/yaml_jinja.py) and a template (templates/riscv-csr.h) code can be easily generated.

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RISC-V ISA Update

October 11, 2020|Updates (riscv.org,spec)

The User ISA and Privileged ISA have been updated to tag draft-20201007-16f5002 in the upstream repo and re-generated as HTML.

The upstream changelog from git is:

  • For emphasis, make MXR/SUM commentary normative
  • Disabling H extension does not ensure illegal instruction traps (#595)
  • Disabling and reenabling extensions makes their state unspecified (#585)
  • Clarify behavior when an extension is disabled (#592)
  • Clarify that “exception code” is used for both exceptions and interrupts
  • Revert “Add VA canonicalization check to Translation Process section”
  • change FCVT.D.S frm to useless (#591)
  • Removed mandate that reserved dynamic rounding modes raise an illegal instruction exception.
  • Revert “Require unimplemented instructions to trap (#582)”
  • Require unimplemented instructions to trap (#582)
  • update OpenHW cores (#578)
  • Fix possible exception list for FCVT.D.S and FCVT.S.D
  • PMP changes don’t need an sfence only when page-based virtual memory is not implemented (#568)
  • Add scontext, hcontext, and mcontext CSRs for Debug (#559)
  • Change “read-only alias” to “read-only copy” (#572)
  • Change “hardwired to other field” to “read-only field” (#571)
  • Rename empty regions to vacant regions for consistency with unpriv spec
  • Clarify that ASIDs are (currently) local to a hart
  • Clarify description of CB format
  • Add marchid for SERV (#569)
  • Remove assembly manual
  • Change “reserved for custom” to “designated for custom” (#566)
  • Improve table of conditions for explicit CSR read/write (#564)
  • Improve table of RAS hints for JALR instructions (#563)
  • Improve table of trap characteristics in introduction (#562)
  • Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3
  • Merge pull request #531 from jhauser-us/jhauser-CSRRules
  • mcounteren only exists if U-mode exists
  • Fix formatting of 2^XLEN
  • Clarify that ASID changes are also immediate
  • Clarify that satp.MODE transitions to/from Bare don’t require SFENCE.VMA
  • Reserve some satp encodings for custom use
  • Fix Sv48 VALEN typo (#551)
  • Clarify effect on unwritten bits for CSRRS/CSRRC
  • Clarify which implicit reads of the translation structures are allowed
  • Add commentary about caching invalid PTEs
  • Clarify what is a side effect of a CSR access (#546)
  • Pmp wording fix (#545)
  • clarify that high counters are RV32I-only
  • Make it explicit that the priv arch requires Zicsr
  • Remove redundant phrase from access-/page-fault text
  • Priority of misaligned load/store address checks is implementation-defined
  • FADD/FSUB can’t raise UF, hence, no PPO dependence
  • Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d8455153f730a0f54
  • Merge pull request #525 from riscv/64-pmp-entries
  • Merge pull request #523 from jhauser-us/jhauser-hstatusVTW
  • Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for now
  • Merge pull request #518 from jhauser-us/jhauser-virtualinstexception
  • Improve description of RV64 *W instructions
  • Clarify that coherent main memory regions use RVWMO or RVTSO
  • Clarify semantics of sfence.vma with rs1 != 0 (#515)
  • Clarify that mtimecmp comparison is unsigned
  • Clarify that various reset events are relative to hart reset
  • Clarify that RV64 accesses to mtime/mtimecmp are atomic
  • Make misaligned exception text more generic than RV32
  • Clarify that the EEI defines misaligned FP ld/st behavior
  • Avoid “should” when describing a mandate
  • Non misleading bit width expression in chapter C (#506)
  • Clarify that FENCE + remote FENCE.I is insufficient for local hart (#503)
  • Add commentary about multi-hit/failing to SFENCE.VMA
  • Clarify offset range in RV64I (#501)
  • RV64 -> RV64I
  • Add note about AUIPC+JALR range in RV64
  • Extensions: List all integer base ISAs (#493)
  • PMP reset values are now platform-defined
  • Add preface section for older version 20191213
  • Clarified overflow behavior of mtime register. Closes #480.
  • Clarify operation of 32-bit AMOs on RV64. Closes #465
  • Clarified description of sstatus. Closes #442
  • Refined definition of WARL. Closes #333.
  • Make clear that “store exception” is “store/AMO exception”.
  • Clarify which exceptions are raised by LR/SC/AMO
  • Clarify that FCVT instructions signal inexact
  • Move VALEN check to the top of Translation Process section
  • Add VA canonicalization check to Translation Process section
  • Only describe scounteren in supervisor chapter
  • The RVWMO is version 2.0 (#483)
  • Update chapters 2 and 7 for Hypervisor v0.6
  • Update hypervisor spec to v0.6
  • Clarify mvendorid.Bank vs. JEDEC bank number
  • ignore write to “controlled” SBE and UBE. (#477)
  • Correct left double quotes (#475)
  • Add Western Digital’s SweRV EL2 and EH2 cores (#474)
  • Clarified that NMIs are interrupts, and should set mcause to have high bit set. Exception code of zero should be returned for systems that don’t distinguish NMI or when cause is unknown. This is not backwards-incompatible given that NMI mcause value was always specified as implementation-defined. Closes #473.
  • Make mtimecmp code sequence legal

RISC-V Draft Bitmanip Spec

September 27, 2020|Updates (riscv.org,spec)

Compiled to HTML from https://github.com/riscv/riscv-bitmanip.

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RISC-V Instructions Quick Reference

May 16, 2020|Updates (isa,quickref)

Added details on how to call instructions from C, listed the CSR instructions, and linked the instruction groups.

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RISC-V CSRs Quick Reference

May 16, 2020|Isa (csr,quickref)

Added details on how to access CSRs from C.

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RISC-V CSRs Quick Reference

May 03, 2020|Updates (registers,quickref)

Updated CSR quick reference page

  • Linked debug registers.
  • Made table sortable.
  • Added feature/extension classification.

RISC-V External Debug Spec

May 03, 2020|Updates (riscv.org,spec)

Compiled to HTML from https://github.com/riscv/riscv-debug-spec.git tex.

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RISC-V Instructions/Extensions Quick Reference

January 21, 2020|Isa (registers,toolchain,quickref)

A few more quick reference pages:

RISC-V Draft Vector Spec

January 04, 2020|Updates (riscv.org,spec)

Compiled to HTML from https://github.com/riscv/riscv-v-spec.

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RISC-V ISA Update

January 02, 2020|Updates (riscv.org,spec)

The User ISA and Privileged ISA have been updated to tag draft-20191228-a6c204f in the upstream repo and re-generated as HTML.

The upstream changelog from git is:

  • Fix FENCE.I cross-reference
  • FENCE.I isn’t in the I base
  • Rephrase awkward sentence
  • Clarify that access exceptions on jump targets are reported on the target
  • Bump version number 20191214-draft
  • A extension v2.1 has been ratified
  • multiplicand, not multiplier, is signed
  • Forgot to include frm as PPO source for FCVT.L[U].S/FCVT.S.L[U]
  • Add pass-through interrupt support and hgeie/hgeip registers
  • Update preface
  • MRET and SRET clear MPRV when leaving M-mode
  • “two-level translation” -> “two-stage translation”
  • Add note about negative htimedelta values
  • tweak
  • satp.PPN’s WARLness is separate from physical address validity
  • Reserve satp fields when MODE=Bare
  • Hypervisor tweaks
  • Convert samepage-commentary blocks to commentary blocks
  • Improve commentary environment page-break behavior
  • hypervisor draft v0.5
  • Merge branch ‘pdonahue-ventana-unspecified’
  • clarify that extra PTE bits are reserved for standard use
  • Describe what we mean by endianness
  • Explicitly remark that SUM/MXR changes don’t need an SFENCE.VMA
  • fix formatting
  • Incorporate feedback from Paul Donahue
  • Incorporate Anthony Coulter’s feedback
  • Address some of Derek’s feedback
  • Fix editing error that allowed FENCE.I in LR/SC sequences
  • Fix typo
  • Incorporate aspects of PR #444
  • Add a description of the reservability PMA.
  • Use effective address consistently
  • Avoid using “virtual address” in normative text of unprivileged spec (#430)
  • Incorporate some of #416 and #418
  • More LR/SC feedback
  • Move CAS code figure to the same page it’s referenced on
  • Introduce “reservation set” terminology
  • More Derek feedback
  • Address Derek’s feedback
  • Constrained loops must use same virtual address for SC
  • Clarify that LR/SC reservation granule mustn’t cross page boundaries
  • Incorporate Dan’s feedback
  • More LR/SC updates
  • Remove page breaks
  • Weaken LR/SC progress guarantee
  • Clarify that pmpcfg.L takes effect even when pmpcfg.A=0
  • Improve supervisor interrupt control section
  • Fix editing error in Atomicity PMA figure caption
  • Update preface
  • Improve interrupt-delegation description
  • Add mcause section label
  • Permit hardwiring of some mideleg bits to 1
  • Refine xepc/xtval WARL requirements
  • Make PMP description consistent with MPRV description
  • Mark misa.G as reserved until the discovery mechansim is defined
  • marchid for c-class core of SHAKTI (#448)
  • Remove outdated commentary
  • mstatus TVM, TW, and TSR are WARL fields
  • Fix outcome description for Figure A.15
  • Closes #359.
  • Like page-table walks, main memory might not support i-fetch
  • Main memory support atomics is a platform mandate, not an ISA one
  • scause must be able to hold the values 0-31
  • Page-table walks are distinct access types for PMA purposes
  • Update contributors
  • Remove released PDFs
  • Add link to archive
  • Relaxed I/O adheres to Appendix A 4.2
  • Merge pull request #441 from Columbus240/I440
  • Define Upper-Half User-Level Timer CSRs for RV32I (#439)

RISC-V Tools Quick Reference

October 29, 2019|Toolchain (toolchain,quickref)

An initial toolchain quick reference.

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RISC-V Registers Quick Reference

October 29, 2019|Isa (registers,quickref)

A few more quick reference pages:

RISC-V Interrupts/Exceptions Quick Reference

August 26, 2019|Isa (interrupts,quickref)

I’ve made an attempt to understand and summarize RISC-V interrupts and exceptions. It mostly covers the machine mode interrupt model, entry and exit procedure. It also looks at supervisor mode, user mode and exceptions.

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RISC-V ISA Update

August 22, 2019|Updates (riscv.org,spec)

The User ISA and Privileged ISA have been updated to tag draft-20190820-22bf021 in the upstream repo and re-generated as HTML.

This will include the ratified 1.11 spec and 1.12 draft.

The upstream changelog from git is:

  • Fix typo in hcounteren privilege
  • hypervisor: add performance counter delta registers
  • Remove pre-PMP-standardization text
  • Use consistent terms for exception types
  • Add @marceg to contributors
  • The execution environment must guarantee harts make progress
  • Fix extension ordering in naming chapter and preface
  • Move N extension into its own chapter in the priv spec
  • More hypervisor updates courtesy of @jhauser-us
  • Fix poor figure placement
  • Update SweRV project URL (#408)
  • Improve description of mtimecmp code sequence
  • Clarify that mtime writes/ticks can also clear MTIP
  • Clarify that mtvec is WARL (#406)
  • Clarify which hints are C.NOP hints and which are C.ADDI hints
  • Merge branch ‘counterinhibit-smt’
  • ECALL and EBREAK don’t retire
  • MPRV affects endianness
  • Remove endianness dependence on PTE.U
  • Fix spelling
  • Update contributors
  • Clarify that, if all PMPs are OFF, all S/U accesses fail
  • Merge pull request #397 from riscv/endianness
  • Clarify PC behavior when XLEN < max supported XLEN
  • State endianness assumption of code example
  • Clarify sign of REM; add commentary
  • Fix bad RV32I chapter formatting
  • Clarify SBE/SFENCE interaction
  • Update contributors
  • add BlackParrot and BaseJump Manycore (#396)
  • Fix preface style
  • Merge pull request #395 from riscv/endianness
  • Bump priv spec to v1.12-draft
  • Hypervisor v0.4 draft
  • Added text to indicate this is the ratified 1.11 version of the spec.
  • Updated preface to indicate this is now ratified spec.
  • Merge pull request #391 from imphil/counter-enable-typo

RISC-V Compile Targets, GCC

June 26, 2019|Toolchain (gcc,base_isa,extensions,abi)

NOTE: Since this was written the riscv-toolchain-conventions document has been released.

Getting started with RISC-V. Compiling for the RISC-V target. This post covers the GCC machine architecture (-march), ABI (-mabi) options and how they relate to the RISC-V base ISA and extensions. It also looks at the multilib configuration for GCC.

Selecting

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About

May 15, 2019|Updates

I’ve setup this this blog to capture information I’ve found useful to develop RISC-V embedded firmware.

My experience is with bare metal RV32EC based systems. Previously I have worked with ARM Cortex-M0 and other processors, so initially I’ll capture the information needed to bootstrap such firmware and the gotchas that come from not yet thinking in RISC-V terms.

Some of the initial planned material is:

  • ISA information presented as easy to reference HTML.
  • Low level information for getting started with the RISC-V architecture.
  • Some evaluation of how RISC-V compares to other architectures.