- Canonical ISA and Extension String
- Base ISA Variants
- Standard ISAs & Alias
- ISA Extensions
- Privilege Levels
- References
NOTE: RISC-V development is rapid and this list can get out of date quickly.
The purpose of this quick reference is to try and get a big picture view as an outsider who wants to know what a rv32x_Zblah is. It won’t always be accurate. There are pointers to the source material.
Canonical ISA and Extension String
There are restrictions on the naming of the combination of ISA and extensions that defines the machine architecture (such as the name passed to gcc’s -march).
- The extension table below is sorted in the canonical order. To construct the name, combine the ISA + the extensions in the canonical order.
e.g.
| ISA | Extensions | Name |
|---|---|---|
| rv32i | a,m,c | rv32imac |
Base ISA Variants
[*]=Working Version of Specification, [+]=Official Specification Repository
| Base ISA | Description | misa | GCC Support | GCC Macro |
New GCC Macro
(gcc 11+) __riscv_arch_test=1 |
|---|---|---|---|---|---|
| rv32e [*] [+] | Reduced version of the 32 bit integer ISA designed for embedded systems | Bit: 4, 0x00000010 | Yes, 8.1.0 |
__riscv __riscv_32e __riscv_xlen=32
|
__riscv_e |
| rv32i [*] [+] | A 32 bit integer ISA sufficient to form a compiler target and to support modern operating system environment | Bit: 8, 0x00000100 | Yes, 7.2.0 |
__riscv __riscv_xlen=32
|
__riscv_i |
| rv64i [*] [+] | A 64 bit integer ISA sufficient to form a compiler target and to support modern operating system environment | Bit: 8, 0x00000100 | Yes, 7.2.0 |
__riscv __riscv_xlen=64
|
__riscv_i |
| rv128 [*] [+] | A variant of the RISC-V ISA supporting a flat 128-bit address space | Bit: 8, 0x00000100 |
__riscv __riscv_xlen=128
|
__riscv_i |
Standard ISAs & Alias
The standard general purpose ISA is rv32g, or rv64g. The ‘g’ is an alias for imafd_Zicsr_Zifencei.
-
The base integer ISA and
mafdextensions are required to run most modern general purpose software. However, those extensions are not strictly needed for embedded and special purpose cores. -
A general purpose operating system will need the CSR and memory fence instructions. They are not included in the base ISA so cores with bare-minimal footprint can be compliant.
ISA Extensions
[*]=Working Version of Specification, [+]=Official Specification Repository
| ID | Extension | misa | Related | GCC Support | GCC Macro |
New GCC Macro
(gcc 11+) __riscv_arch_test=1 |
|---|---|---|---|---|---|---|
| M [*] [+] | Integer Multiply/Divide extension | Bit: 12, 0x00001000 | Zmmul | Yes, from 7.2.0. |
|
__riscv_m |
| A [*] [+] | Atomic extension | Bit: 0, 0x00000001 | Zam | Yes, from 7.2.0. |
|
__riscv_a |
| F [*] [+] | Single-precision floating-point extension | Bit: 5, 0x00000020 | Zfinx | Yes, from 7.2.0. |
__riscv_float_abi_single __riscv_flen=32
|
__riscv_f |
| D [*] [+] | Double-precision floating-point extension | Bit: 3, 0x00000008 | Zdinx | Yes, from 7.2.0. |
__riscv_float_abi_double __riscv_flen=64
|
__riscv_d |
| Q [*] [+] | Quad-precision floating-point extension | Bit: 16, 0x00010000 |
__riscv_flen=128
|
|||
| C [*] [+] | Compressed Instructions Extension | Bit: 2, 0x00000004 | Yes, from 7.2.0. |
|
__riscv_c | |
| L | Decimal Floating-Point extension | Bit: 11, 0x00000800 |
|
|||
| B [*] [+] | Bit-Manipulation extension | Bit: 1, 0x00000002 | Zba Zbb Zbc Zbs Zbkx Zbkc Zbkb | Yes, from 12.0. |
|
|
| J [*] [+] | Dynamically Translated Languages extension | Bit: 9, 0x00000200 | Zjid |
|
||
| T | Transactional Memory extension | Bit: 21, 0x00200000 |
|
|||
| P [*] [+] | Packed-SIMD extension | Bit: 15, 0x00008000 |
|
__riscv_p | ||
| V [*] [+] | Vector extension | Bit: 21, 0x00200000 | In development (9.2.0-rvv 10.1.0-rvv). |
__riscv_vector __riscv_v_min_vlen __riscv_v_elen __riscv_v_elen_fp
|
__riscv_v | |
| N | User-level interrupts supported | Bit: 13, 0x00002000 |
|
|||
| Counters | Performance Counter CSRs |
|
||||
| G | Additional standard extensions present | Bit: 6, 0x00000040 |
|
|||
| H [*] [+] | Hypervisor extension | Bit: 7, 0x00000080 |
|
|||
| X | Non-standard extensions present | Bit: 23, 0x00800000 |
|
|||
| Zam | Standard Extension for Misaligned Atomics | A |
|
|||
| Zawrs [+] | Wait-on-Reservation-Set extension (low power mode) |
|
||||
| Zba [*] [+] | Bit-manipulation: Address generation instructions | B | Yes, from 12.0. |
|
__riscv_zba | |
| Zbb [*] [+] | Basic bit-manipulation | B | Yes, from 12.0. |
|
__riscv_zbb | |
| Zbc [*] [+] | Bit-manipulation: Carry-less multiplication | B | Yes, from 12.0. |
|
__riscv_zbc | |
| Zbkb [*] [+] | Bit-manipulation for Cryptography | B |
|
|||
| Zbkc [*] [+] | Bit-manipulation: Carry-less multiplication for Cryptography | B |
|
|||
| Zbkx [*] [+] | Bit-manipulation: Crossbar permutations | B |
|
|||
| Zbs [*] [+] | Bit-manipulation: Single-bit instructions | B | Yes, from 12.0. |
|
__riscv_zbs | |
| Zce [+] | Code Size Reduction |
|
||||
| Zdinx | Standard Extension for Double Floating-Point in Integer Registers | D |
|
|||
| Zfh [*] [+] | Standard Extension for 16-bit Half-Precision Binary Floating-Point Instructions | Zhinx, Zhinxmin |
|
__riscv_zfh | ||
| Zfinx [*] [+] | Standard Extension for Floating-Point in Integer Registers | F |
|
|||
| Zhinx | Standard Extension for Half Precision Floating-Point in Integer Registers | Zfh |
|
|||
| Zhinxmin | Zfh |
|
||||
| Zicbo [*] [+] | Cache Management Operations for RISC-V | Zicbom Zicboz Zicbop |
|
|||
| Zicbom [*] [+] | Cache-Block Management Instructions | Zicbo |
|
|||
| Zicbop [*] [+] | Cache-Block Prefetch Instructions | Zicbo |
|
|||
| Zicboz [*] [+] | Cache-Block Zero Instructions | Zicbo |
|
|||
| Zicsr [*] [+] | Control and Status Register (CSR) Instructions |
|
__riscv_zicsr | |||
| Zifencei [*] [+] | Instruction-Fetch Fence |
|
__riscv_zifencei | |||
| Zihintntl [*] [+] | Non-Temporal Locality Hints |
|
||||
| Zihintpause [*] [+] | Pause Hint |
|
||||
| Zjid [+] | Temporary Proposal for Instruction/Data synchronization for JIT. | J |
|
|||
| Zk | Scalar Crypto Specification | Zkn Zks Zkr Zkne Zknd Zknh Zksed Zksh Zkt |
|
|||
| Zkn | Zk |
|
||||
| Zknd | Zk |
|
||||
| Zkne | Zk |
|
||||
| Zknh | Zk |
|
||||
| Zkr | Zk |
|
||||
| Zks | Zk |
|
||||
| Zksed | Zk |
|
||||
| Zksh | Zk |
|
||||
| Zkt | Zk |
|
||||
| Zmmul | Multiply Without Divide | M |
|
|||
| Ztso [*] [+] | Standard Extension for Total Store Ordering |
|
||||
| Zve | Vector Extensions for Embedded Processors | Zve32x Zve32f Zve64x Zve64f Zve64d |
|
|||
| Zve32f | VLEN>=32 bits, 32 Bit Float Vector | Zve |
|
|||
| Zve32x | VLEN>=32 bits, Integer Only Vector | Zve |
|
|||
| Zve64d | VLEN>=64 bits, 64 Bit Float Support Vector | Zve |
|
|||
| Zve64f | VLEN>=64 bits, 32 Bit Float Support Vector | Zve |
|
|||
| Zve64x | VLEN>=64 bits, Integer Only Vector | Zve |
|
|||
| Zvl | Minimum Vector Length Standard Extensions | V Zvl32b Zvl64b Zvl128b Zvl256b Zvl512b Zvl1024b |
|
|||
| Zvl1024b | VLEN>=1024 bits | Zvl |
|
|||
| Zvl128b | VLEN>=128 bits | Zvl |
|
|||
| Zvl256b | VLEN>=256 bits | Zvl |
|
|||
| Zvl32b | VLEN>=32 bits (default) | Zvl |
|
|||
| Zvl512b | VLEN>=512 bits | Zvl |
|
|||
| Zvl64b | VLEN>=64 bits | Zvl |
|
Privilege Levels
| ID | Mode | misa |
|---|---|---|
| m | machine | |
| s | supervisor | Bit: 18, 0x00040000 |
| u | user | Bit: 20, 0x00100000 |
| d | debug |
References
- RISC-V GitHub: Toolchain Conventions
- RISC-V Wiki: Extensions
- RISC-V C-ABI
- Manual: Base ISA Variants
- Manual: ISA Extensions
- Manual: Privilege Levels
- GCC Source: riscv.opt
- GCC Source: riscv-common.cc, supported extensions.
- GCC Source: riscv-opts.h, built-in macros.
- GCC Source: riscv-c.cc, built-in macros.
- GCC Manual: RISC-V-Options
- GCC Change Log:
- GCC Articles
- Other Papers