RISC-V ISA Instruction Quick Reference Update
March 03, 2024 (riscv.org,spec,html)
The Instructions Quickref has been updated to match the changes made for Compiler Explorer.
The opcode references are generated from opcodes.yaml which is generated by convert_opcodes.rb in https://github.com/five-embeddev/riscv-docs-html/tree/gh_pages.
RISC-V ISA Reference for Compiler Explorer
November 15, 2023 (riscv.org,spec,html)
Compiler explorer now includes RISC-V opcode references for the rv64 targets, following my pull pull request and initial work by Siyao.
The updated files are:
- etc/scripts/docenizers/docenizer-riscv64.py: Generator, converts
yamltots. - lib/asm-docs/generated/asm-docs-riscv64.ts: The generated opcode documentation.
The opcode references are generated from opcodes.yaml which is generated by convert_opcodes.rb in https://github.com/five-embeddev/riscv-docs-html/tree/gh_pages.
The opcode decriptions are automatically extracted from the ISA user manual in HTML format. For example the description for sd is extracted from the Load and Store Instructions section.
To generate the data run these commands in the compiler explorer repo:
cd compiler-explorer/etc/scripts/docenizers/
./docenizer-riscv64.py \
-i https://five-embeddev.github.io/riscv-docs-html/opcodes.yaml \
-o ../../../lib/asm-docs/generated/asm-docs-riscv64.ts
RISC-V ISA Manuals to HTML
July 31, 2023 (riscv.org,spec,html,docker)
The User ISA and Privileged ISA have been are converted to HTML from TEX on the upstream repo.
The latest upstream versions have recently been converted to asciidoc, but the legacy versions that were used to generate HTML on this site are converted from the older TEX.
In theory converting tex should be as simple as running a conversion tool such as pandoc or latex2html but without some optimization that gives quite ugly results - in particular for tables and diagrams.
The set of scripts that this blog uses to optimize the pandoc output has been uploaded to https://github.com/five-embeddev/riscv-docs-html. A Dockerfile is used to configure a build environment with pandoc and asciidoctor and the other tools used to do the conversion.
A set of static html github pages have been exported here, https://five-embeddev.github.io/riscv-docs-html/. They HTML is identical, but it lacks the side navigation menu and css style used by this site.
These scripts are also used to create the opcodes.yaml and csr.yaml data files used by the Instruction Quick Reference and CSR Quick Reference on this site.
More info on that will be posted later.
RISC-V Interrupts/Exceptions Quick Reference
May 11, 2023 (interrupts,quickref)
A fix has been made to the Interrupts/Exceptions Quick Reference to clarify that mstatus.mpp is set to the the least-privileged supported mode on mret. The local version of Machine-Level ISA has been updated to the Priv-v1.12 source as this is the current version on https://riscv.org/technical/specifications/. References to the depreciated user mode interrupts and the n extension were also removed.
CSR Quick Reference Update
May 04, 2023 (registers,csr,quickref)
The CSR quick reference list was updated:
- Cross references to manuals.
- Details for some fields.
RISC-V ISA Manual Update
The User ISA and Privileged ISA have been updated to tag Priv-1.12 in the upstream repo and re-generated as HTML.
- Updated to official release branch (Priv-1.12)
- Added links to source documents, source version.
The upstream changelog from git is:
RISC-V Debug Spec Update
April 29, 2023 (riscv.org,spec)
The generated html for the “RISC-V External Debug Support” spec has been updated.
- Reverted to official release branch (0.13.2)
- Many tex->html conversion errors fixed.
- Added links to source documents, source version.
RISC-V ISA Update
August 18, 2022 (riscv.org,spec,quickref)
A few upates:
- Update ISA & extensions to many recent updated extensions.
- Update to latest Vector Spec and Bit-manipulation Spec.
RISC-V ISA Update
October 11, 2020 (riscv.org,spec)
The User ISA and Privileged ISA have been updated to tag draft-20201007-16f5002 in the upstream repo and re-generated as HTML.
The upstream changelog from git is:
RISC-V Draft Bitmanip Spec
September 27, 2020 (riscv.org,spec)
Compiled to HTML from https://github.com/riscv/riscv-bitmanip.
RISC-V Instructions Quick Reference
Added details on how to call instructions from C, listed the CSR instructions, and linked the instruction groups.
RISC-V CSRs Quick Reference
May 03, 2020 (registers,quickref)
Updated CSR quick reference page
- Linked debug registers.
- Made table sortable.
- Added feature/extension classification.
RISC-V Draft Vector Spec
January 04, 2020 (riscv.org,spec)
Compiled to HTML from https://github.com/riscv/riscv-v-spec.
RISC-V ISA Update
January 02, 2020 (riscv.org,spec)
The User ISA and Privileged ISA have been updated to tag draft-20191228-a6c204f in the upstream repo and re-generated as HTML.
The upstream changelog from git is:
RISC-V ISA Update
August 22, 2019 (riscv.org,spec)
The User ISA and Privileged ISA have been updated to tag draft-20190820-22bf021 in the upstream repo and re-generated as HTML.
This will include the ratified 1.11 spec and 1.12 draft.
The upstream changelog from git is:
About
May 15, 2019
I’ve setup this this blog to capture information I’ve found useful to develop RISC-V embedded firmware.
My experience is with bare metal RV32EC based systems. Previously I have worked with ARM Cortex-M0 and other processors, so initially I’ll capture the information needed to bootstrap such firmware and the gotchas that come from not yet thinking in RISC-V terms.
Some of the initial planned material is:
- ISA information presented as easy to reference HTML.
- Low level information for getting started with the RISC-V architecture.
- Some evaluation of how RISC-V compares to other architectures.