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An Embedded RISC-V Blog

Baremetal Vectored Interrupts in C for RISC-V

September 25, 2021 (toolchain,baremetal,C)

An example of using vectored interrupts in C.

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Baremetal Timer Driver in C for RISC-V

September 24, 2021 (toolchain,baremetal,C)

An example of a timer driver in C has been added.

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Baremetal Startup in C for RISC-V

September 24, 2021 (toolchain,baremetal,C)

An example of a startup code in C.

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Baremetal Timer Driver in C++ for RISC-V

August 13, 2021 (toolchain,baremetal,C++)

An example of a timer driver.

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Baremetal Interrupt in C++ for RISC-V

August 13, 2021 (toolchain,baremetal,C++)

An example of using interrupts.

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Baremetal Startup Code in C++ for RISC-V

April 13, 2021 (toolchain,baremetal,C++)

An example of baremetal bootstrap code for RISC-V in C++.

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RISC-V CSR Access

November 18, 2020 (registers,code,baremetal,quickref)

For baremetal programming I’ll often need to access CSRs, e.g. mstatus.mie for critical sections, mcause in interrupts handlers, etc. Defining function wrappers for accessing these registers creates easier to understand code, however writing these wrappers is pretty tedious.

The quick reference on this blog is generated from a YAML description (csr.yaml). Using that with a web template engine script (generators/yaml_jinja.py) and a template (templates/riscv-csr.h) code can be easily generated.

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