Address	Name	Description	Page
0x00	BYPASS	JTAG recommends this encoding
0x01	IDCODE	JTAG recommends this encoding
0x10	DTM Control and Status (dtmcs)	For Debugging
0x11	Debug Module Interface Access (dmi)	For Debugging
0x12	Reserved (BYPASS)	Reserved for future RISC-V debugging
0x13	Reserved (BYPASS)	Reserved for future RISC-V debugging
0x14	Reserved (BYPASS)	Reserved for future RISC-V debugging
0x15	Reserved (BYPASS)	Reserved for future RISC-V standards
0x16	Reserved (BYPASS)	Reserved for future RISC-V standards
0x17	Reserved (BYPASS)	Reserved for future RISC-V standards
0x1f	BYPASS	JTAG requires this encoding

IDCODE (at 0x01)

[idcode] This register is selected (in IR) when the TAP state machine is reset. Its definition is exactly as defined in IEEE Std 1149.1-2013.

This entire register is read-only.

Field	Description	Access	Reset
[Version] |Version|	Identifies the release version of this part.	R	Preset
[PartNumber] |PartNumber|	Identifies the designer’s part number of this part.	R	Preset
[ManufId] |ManufId|	Identifies the designer/manufacturer of this part. Bits 6:0 must be bits 6:0 of the designer/manufacturer’s Identification Code as assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 count of the number of continuation characters (0x7f) in that same Identification Code.	R	Preset

DTM Control and Status (dtmcs, at 0x10)

[dtmcs] The size of this register will remain constant in future versions so that a debugger can always determine the version of the DTM.

Field	Description	Access	Reset
[dmihardreset] |dmihardreset|	Writing 1 to this bit does a hard reset of the DTM, causing the DTM to forget about any outstanding DMI transactions. In general this should only be used when the Debugger has reason to expect that the outstanding DMI transaction will never complete (e.g. a reset condition caused an inflight DMI transaction to be cancelled).	W1	-
[dmireset] |dmireset|	Writing 1 to this bit clears the sticky error state and allows the DTM to retry or complete the previous transaction.	W1	-
[idle] |idle|	This is a hint to the debugger of the minimum number of cycles a debugger should spend in Run-Test/Idle after every DMI scan to avoid a ‘busy’ return code (dmistatof 3). A debugger must still check dmistatwhen necessary. 0: It is not necessary to enter Run-Test/Idle at all. 1: Enter Run-Test/Idle and leave it immediately. 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. And so on.	R	Preset
[dmistat] |dmistat|	0: No error. 1: Reserved. Interpret the same as 2. 2: An operation failed (resulted in opof 2). 3: An operation was attempted while a DMI access was still in progress (resulted in opof 3).	R	0
[abits] |abits|	The size of addressin dmi.	R	Preset
[version] |version|	0: Version described in spec version 0.11. 1: Version described in spec version 0.13. 15: Version not described in any available version of this spec.	R	1

Debug Module Interface Access (dmi, at 0x11)

[dmi] This register allows access to the Debug Module Interface (DMI).

In Update-DR, the DTM starts the operation specified in opunless the current status reported in opis sticky.

In Capture-DR, the DTM updates datawith the result from that operation, updating opif the current opisn’t sticky.

See Section [dmiaccess] and Table [tab:memread] for examples of how this is used.

The still-in-progress status is sticky to accommodate debuggers that batch together a number of scans, which must all be executed or stop as soon as there’s a problem.

For instance a series of scans may write a Debug Program and execute it. If one of the writes fails but the execution continues, then the Debug Program may hang or have other unexpected side effects.

Field	Description	Access	Reset
[address] |address|	Address used for DMI access. In Update-DR this value is used to access the DM over the DMI.	R/W	0
[data] |data|	The data to send to the DM over the DMI during Update-DR, and the data returned from the DM as a result of the previous operation.	R/W	0
[op] |op|	When the debugger writes this field, it has the following meaning: 0: Ignore dataand address. (nop) Don’t send anything over the DMI during Update-DR. This operation should never result in a busy or error response. The address and data reported in the following Capture-DR are undefined. 1: Read from address. (read) 2: Write datato address. (write) 3: Reserved. When the debugger reads this field, it means the following: 0: The previous operation completed successfully. 1: Reserved. 2: A previous operation failed. The data scanned into dmiin this access will be ignored. This status is sticky and can be cleared by writing dmiresetin dtmcs. This indicates that the DM itself responded with an error. There are no specified cases in which the DM would respond with an error, and DMI is not required to support returning errors. 3: An operation was attempted while a DMI request is still in progress. The data scanned into dmiin this access will be ignored. This status is sticky and can be cleared by writing dmiresetin dtmcs. If a debugger sees this status, it needs to give the target more TCK edges between Update-DR and Capture-DR. The simplest way to do that is to add extra transitions in Run-Test/Idle.	R/W	0

BYPASS (at 0x1f)

[bypass] 1-bit register that has no effect. It is used when a debugger does not want to communicate with this TAP.

This entire register is read-only.