Five EmbedDev

An Embedded RISC-V Blog

Change Log

Preface

1. Introduction

2. Reading Order
- - 2.0.1. Halt/Resume
  - 2.0.2. Abstract Register Access
  - 2.0.3. Program Buffer
  - 2.0.4. JTAG Debug Transport Module
  - 2.0.5. System Bus Master
  - 2.0.6. Reset
  - 2.0.7. Security
  - 2.0.8. Triggers
  - 2.0.9. Serial Ports

3. System Overview

4. Debug Module (DM)

5. RISC-V Debug

6. Trigger Module

7. Debug Transport Module (DTM)

8. JTAG Debug Transport Module

Hardware Implementations

Debugger Implementation

RISC-V External Debug Support , task_group_vote-4-g4e0bb0f 2019/03/25

2 Reading Order

This section describes the minimal parts of the spec required to understand a given piece of functionality. It’s still best to read the whole thing, but it might help you get started better than reading it all start to finish. No matter what you want to learn about, it’s best to read Section [overview] first.

2.0.1 Halt/Resume

Sections [dmi], [selectingharts], [haltcontrol], [dmcontrol], [dmstatus], [haltsum], [deb:halt].

2.0.2 Abstract Register Access

Sections [abstractcommands], [abstractcs], [command], [data0], [deb:abstractreg].

2.0.3 Program Buffer

Sections [programbuffer], [progbufcs], [progbuf0], [access register], [debugmode], [deb:regprogbuf], [deb:mrprogbuf].

2.0.4 JTAG Debug Transport Module

Sections [dtm], [jtagdtm], [dbusaccess].

2.0.5 System Bus Master

Sections [systembusaccess], [sbcs], [sbaddress0], [sbaddress1], [sbaddress2], [sbdata0], [sbdata1], [sbdata2], [sbdata3], [deb:mrsysbus].

2.0.6 Reset

TODO

2.0.7 Security

TODO

2.0.8 Triggers

TODO

2.0.9 Serial Ports

TODO

© RISC-V Foundation, CC BY 4.0. Coverted to HTML from reading_order.tex(task_group_vote-4-g4e0bb0f) using Pandoc. For the official specifications refer to riscv.org.