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About
Preface
1.
Introduction
2.
RV32I Base Integer Instruction Set, Version 2.1
3.
Zifencei Instruction-Fetch Fence, Version 2.0
4.
Zihintpause Pause Hint, Version 2.0
5.
RV32E and RV64E Base Integer Instruction Sets, Version 2.0
6.
RV64I Base Integer Instruction Set, Version 2.1
7.
RV128I Base Integer Instruction Set, Version 1.7
8.
M Standard Extension for Integer Multiplication and
9.
A Standard Extension for Atomic Instructions, Version 2.1
10.
Zicsr, Control and Status Register (CSR) Instructions, Version 2.0
11.
Zicntr and Zihpm Counters
12.
F Standard Extension for Single-Precision Floating-Point,
13.
D Standard Extension for Double-Precision Floating-Point,
14.
Q Standard Extension for Quad-Precision Floating-Point,
15.
Zfh and Zfhmin Standard Extensions for Half-Precision Floating-Point,
16.
RVWMO Memory Consistency Model, Version 2.0
17.
C Standard Extension for Compressed Instructions, Version
18.
B Standard Extension for Bit Manipulation, Version 0.0
19.
J Standard Extension for Dynamically Translated Languages, Version 0.0
20.
P Standard Extension for Packed-SIMD Instructions,
21.
V Standard Extension for Vector Operations, Version 1.0
22.
Zam Standard Extension for Misaligned Atomics, v0.1
23.
Zfinx, Zdinx, Zhinx, Zhinxmin: Standard Extensions for Floating-Point in Integer Registers, Version 1.0
24.
Ztso Standard Extension for Total Store Ordering, Version 1.0
25.
RV32/64G Instruction Set Listings
26.
Extending RISC-V
27.
ISA Extension Naming Conventions
28.
History and Acknowledgments
CSR Dependency Tracking Granularity
Source and Destination Register Listings
RVWMO Explanatory Material, Version 0.1
Formal Memory Model Specifications, Version 0.1
Formal Axiomatic Specification in Alloy
Formal Axiomatic Specification in Herd
An Operational Memory Model
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , isa-449cd0c 2023/04/18
Instruction listing for RISC-V