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An Embedded RISC-V Blog

Machine Readable Specification Data

September 10, 2021 (registers,spec,interrupts,opcodes)

As RISC-V is a new architecture so there will be new development at all layers of the software and hardware stack. Rather than write code based on human language specifications from scratch, a smarter way to work can be to translate a machine readable specification to code.

“Machine Readable” does not need to be an all encompassing formal model of the architecture, there are many convenient formats such as csv, yaml, xml and json that can be parsed and transformed using the packages available in most scripting languages.


CMake Cross Compilation for RISC-V Targets

March 20, 2021 (toolchain,baremetal)

An example of cross compiling a baremetal program to RISC-V with CMake.


RISC-V Compile Targets, GCC

February 09, 2021 (gcc,base_isa,extensions,abi)

Note to self: When compiling the riscv-toolchain for embedded systems, set the configure options!

The toolchain can be cloned from the RISC-V official github. Once the dependencies are installed it’s straight forward to compile.

$ git clone --recursive


RISC-V Tools Quick Reference

October 29, 2019 (toolchain,quickref)

An initial toolchain quick reference.


RISC-V Compile Targets, GCC

June 26, 2019 (gcc,base_isa,extensions,abi)

NOTE: Since this was written the riscv-toolchain-conventions document has been released.

Getting started with RISC-V. Compiling for the RISC-V target. This post covers the GCC machine architecture (-march), ABI (-mabi) options and how they relate to the RISC-V base ISA and extensions. It also looks at the multilib configuration for GCC.