The User ISA and Privileged ISA have been updated to tag draft-20190820-22bf021 in the upstream repo and re-generated as HTML.
This will include the ratified 1.11 spec and 1.12 draft.
The upstream changelog from git is:
- Fix typo in hcounteren privilege
- hypervisor: add performance counter delta registers
- Remove pre-PMP-standardization text
- Use consistent terms for exception types
- Add @marceg to contributors
- The execution environment must guarantee harts make progress
- Fix extension ordering in naming chapter and preface
- Move N extension into its own chapter in the priv spec
- More hypervisor updates courtesy of @jhauser-us
- Fix poor figure placement
- Update SweRV project URL (#408)
- Improve description of mtimecmp code sequence
- Clarify that mtime writes/ticks can also clear MTIP
- Clarify that mtvec is WARL (#406)
- Clarify which hints are C.NOP hints and which are C.ADDI hints
- Merge branch ‘counterinhibit-smt’
- ECALL and EBREAK don’t retire
- MPRV affects endianness
- Remove endianness dependence on PTE.U
- Fix spelling
- Update contributors
- Clarify that, if all PMPs are OFF, all S/U accesses fail
- Merge pull request #397 from riscv/endianness
- Clarify PC behavior when XLEN < max supported XLEN
- State endianness assumption of code example
- Clarify sign of REM; add commentary
- Fix bad RV32I chapter formatting
- Clarify SBE/SFENCE interaction
- Update contributors
- add BlackParrot and BaseJump Manycore (#396)
- Fix preface style
- Merge pull request #395 from riscv/endianness
- Bump priv spec to v1.12-draft
- Hypervisor v0.4 draft
- Added text to indicate this is the ratified 1.11 version of the spec.
- Updated preface to indicate this is now ratified spec.
- Merge pull request #391 from imphil/counter-enable-typo