The User ISA and Privileged ISA have been updated to tag draft-20201007-16f5002 in the upstream repo and re-generated as HTML.

The upstream changelog from git is:

• For emphasis, make MXR/SUM commentary normative
• Disabling H extension does not ensure illegal instruction traps (#595)
• Disabling and reenabling extensions makes their state unspecified (#585)
• Clarify behavior when an extension is disabled (#592)
• Clarify that “exception code” is used for both exceptions and interrupts
• Revert “Add VA canonicalization check to Translation Process section”
• change FCVT.D.S frm to useless (#591)
• Removed mandate that reserved dynamic rounding modes raise an illegal instruction exception.
• Revert “Require unimplemented instructions to trap (#582)”
• Require unimplemented instructions to trap (#582)
• update OpenHW cores (#578)
• Fix possible exception list for FCVT.D.S and FCVT.S.D
• PMP changes don’t need an sfence only when page-based virtual memory is not implemented (#568)
• Add scontext, hcontext, and mcontext CSRs for Debug (#559)
• Change “read-only alias” to “read-only copy” (#572)
• Change “hardwired to other field” to “read-only field” (#571)
• Rename empty regions to vacant regions for consistency with unpriv spec
• Clarify that ASIDs are (currently) local to a hart
• Clarify description of CB format
• Add marchid for SERV (#569)
• Remove assembly manual
• Change “reserved for custom” to “designated for custom” (#566)
• Improve table of conditions for explicit CSR read/write (#564)
• Improve table of RAS hints for JALR instructions (#563)
• Improve table of trap characteristics in introduction (#562)
• Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3
• Merge pull request #531 from jhauser-us/jhauser-CSRRules
• mcounteren only exists if U-mode exists
• Fix formatting of 2^XLEN
• Clarify that ASID changes are also immediate
• Clarify that satp.MODE transitions to/from Bare don’t require SFENCE.VMA
• Reserve some satp encodings for custom use
• Fix Sv48 VALEN typo (#551)
• Clarify effect on unwritten bits for CSRRS/CSRRC
• Clarify which implicit reads of the translation structures are allowed
• Add commentary about caching invalid PTEs
• Clarify what is a side effect of a CSR access (#546)
• Pmp wording fix (#545)
• clarify that high counters are RV32I-only
• Make it explicit that the priv arch requires Zicsr
• Remove redundant phrase from access-/page-fault text
• Priority of misaligned load/store address checks is implementation-defined
• FADD/FSUB can’t raise UF, hence, no PPO dependence
• Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d8455153f730a0f54
• Merge pull request #525 from riscv/64-pmp-entries
• Merge pull request #523 from jhauser-us/jhauser-hstatusVTW
• Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for now
• Merge pull request #518 from jhauser-us/jhauser-virtualinstexception
• Improve description of RV64 *W instructions
• Clarify that coherent main memory regions use RVWMO or RVTSO
• Clarify semantics of sfence.vma with rs1 != 0 (#515)
• Clarify that mtimecmp comparison is unsigned
• Clarify that various reset events are relative to hart reset
• Clarify that RV64 accesses to mtime/mtimecmp are atomic
• Make misaligned exception text more generic than RV32
• Clarify that the EEI defines misaligned FP ld/st behavior
• Avoid “should” when describing a mandate
• Non misleading bit width expression in chapter C (#506)
• Clarify that FENCE + remote FENCE.I is insufficient for local hart (#503)
• Add commentary about multi-hit/failing to SFENCE.VMA
• Clarify offset range in RV64I (#501)
• RV64 -> RV64I
• Add note about AUIPC+JALR range in RV64
• Extensions: List all integer base ISAs (#493)
• PMP reset values are now platform-defined
• Add preface section for older version 20191213
• Clarified overflow behavior of mtime register. Closes #480.
• Clarify operation of 32-bit AMOs on RV64. Closes #465
• Clarified description of sstatus. Closes #442
• Refined definition of WARL. Closes #333.
• Make clear that “store exception” is “store/AMO exception”.
• Clarify which exceptions are raised by LR/SC/AMO
• Clarify that FCVT instructions signal inexact
• Move VALEN check to the top of Translation Process section
• Add VA canonicalization check to Translation Process section
• Only describe scounteren in supervisor chapter
• The RVWMO is version 2.0 (#483)
• Update chapters 2 and 7 for Hypervisor v0.6
• Update hypervisor spec to v0.6
• Clarify mvendorid.Bank vs. JEDEC bank number
• ignore write to “controlled” SBE and UBE. (#477)
• Correct left double quotes (#475)
• Add Western Digital’s SweRV EL2 and EH2 cores (#474)
• Clarified that NMIs are interrupts, and should set mcause to have high bit set. Exception code of zero should be returned for systems that don’t distinguish NMI or when cause is unknown. This is not backwards-incompatible given that NMI mcause value was always specified as implementation-defined. Closes #473.
• Make mtimecmp code sequence legal