The User ISA and Privileged ISA have been updated to tag Priv-1.12 in the upstream repo and re-generated as HTML.

• Updated to official release branch (Priv-1.12)
• Added links to source documents, source version.

The upstream changelog from git is:

• bump priv version
• Relax Svpbmt sequence slightly
• Add FLH, FSH to defined transformed instructions for H extension (#792)
• priv spec version 20211202
• boldface ratified extensions
• Clarify that henvcfg.PBMTE is read-only zero if Svpbmt is not implemented
• Clarify that PBMTE is read-only zero if Svpbmt is not implemented
• fix typo
• Permit speculative execution of HLV/HSV; reset hgatp.MODE, satp.MODE
• Fix Travis build status image URL
• Rework the description of exceptions for Svinval (#786)
• Change H extension to version 1.0 (#787)
• Interrupts and exceptions are different things. (#788)
• Priv specs are ratified
• Add menvcfg.PBMTE / henvcfg.PBMTE
• Remark that Svnapot and Svpbmt require Sv39
• Move SFENCE.VMA/satp.MODE remark to better location
• Clarify that implicit reads of CSRs return same value as explicit reads (#783)
• Fix typo
• Add VS field
• Split RV32 [v]sstatus figures into two rows
• Add Hazard3 to open-source marchid list (#784)
• Fix typo
• Specify a sequence to regain coherence wrt. mismatched PBMTs
• Avoid use of “timebase”
• Clarify definition of [m]time CSR
• Merge branch ‘jhauser-us-jhauser-2021-CSRFieldMods’
• Clarify when SFENCE.VMA/HFENCE.GVMA need be executed
• Extension is “implemented”, not “enabled” (in Svinval) (#780)
• Explain why mstatus.TVM doesn’t affect vsatp, HFENCE.VVMA (#779)
• H extension requires page-based address translation (#778)
• Non-normatively remark that high-order PPN bits aren’t ignored
• Revert “Separate transformation for HLV instructions (#777)”
• Fix typo
• Separate transformation for HLV instructions (#777)
• Memory access traps may write zero to stval (#776)
• Accesses to pages with mismatched attrs are I/O and memory wrt FENCE (#774)
• Rename hstatus.HU (#770)
• Allow more bits of hideleg to be writable (#772)
• Clarify condition when virtual instruction trap will occur (#773)
• CSR mideleg masks hideleg, hip, and hie (#771)
• Rewrite most instances of “hardwire” as “read-only” (#768)
• Remove trailing whitespace from a.tex (#767)
• Document version 20211105-signoff
• Further relax PMP/address-translation caching interactions
• Merge pull request #763 from riscv/virt-mem-extensions
• Add Sv57 and Sv57x4
• Merge branch ‘master’ of github.com:riscv/riscv-isa-manual
• Back to draft status
• Define the Zicntr and Zihpm extensions
• Improve text in Zicntr section
• Document version 20211028-signoff
• Incorporate Steve’s feedback
• No valid LR/SC reservation upon reset
• Fix editing error in mtval/stval definition
• Clarify order in which PMP CSRs must be implemented
• Fix permissions of *envcfg CSRs
• Improve description of FENCE.TSO
• Add example to clarify mip.SEIP behavior
• Bump priv version number
• Priv-1.12 spec for public review
• JohnH is an editor of the priv spec
• RISC-V Foundation -> RISC-V International
• Freeze the hypervisor extension, version 1.0.0-rc (#739)
• mip.MSIP and mie.MSIE may be hardwired zeros (#738)
• Hypervisor extension requires page-based address translation (#737)
• Fix apparent typo re hpmcounter*h (#735)
• State behavior of uncacheable accesses to cacheable locations
• Clarify that WARL fields contain legal values after reset (#734)
• Rename STCE to STCD to reverse its polarity
• Generalize SSIP to support forthcoming interrupt controllers (#726)
• Speculative implicit reads, v2 (#724)
• Fix a typo in Figure A.13. (#733)
• Merge pull request #727 from riscv/mseccfg
• Make virtual instruction exceptions more consistent for VU mode (#730)
• Pedantically clarify behavior of writing lo/hi parts of counters
• Remove errant preface entry
• Clarify widths of privileged CSRs (#728)
• Revert “Replace “EEI” with “execution environment” (#723)”
• Add preface entry
• Designate some of SYSTEM opcode for custom use
• Add mconfigptr CSR (#697)
• Replace “EEI” with “execution environment” (#723)
• Fix (again) non-normative CSR side-effect text
• Remove historical remark on MRET definition
• Fix non-normative text about CSR ordering (#720)
• Add marchid for Hummingbirdv2 E203 (#664)
• Update H chapter table of synchronous exception priorities (#717)
• Tweak table of synchronous exception priorities (#716)
• Make explicit the priorities of synch. exceptions of H extension (#711)
• Clarify priorities of synchronous exceptions (#715)
• stval already cannot be zero on breakpoints, misaligned addresses (#714)
• VS mode should not see exception code 10 (#712)
• Merge branch ‘jhauser-us-jhauser-2021-HBaseI’
• Corrections to mstatus in hypervisor chapter (#710)
• Minor improvements to text for virtual instruction exceptions (#709)
• Clarify when mstatus.FS may be hardwired zero (#707)
• Interrupt conditions are also evaluated on falling edges
• Generalize interrupt trap condition evaluation conditions (#705)
• Clarify that RV64 accesses to mtime[cmp] are atomic
• State that misa.F does not affect mstatus.FS
• Improve rules for virtual instruction exceptions, again (#703)
• Clarify mepc invalid address conversion
• Improve description of interrupt traps (#701)
• Merge branch ‘jhauser-us-jhauser-2021-extStats’
• Clarify that SFENCE.VMA isn’t required for Sbare
• Fix b6cade07034d39e65134a879a5c3369d50e0df0e
• Remove N extension chapter for now
• CSR instead of field (#669)
• Add non-normative text about VIPT caches not being exposed
• Remove concept of hard reset from normative text
• Add marchid for XiangShan (#661)
• PMP RWX are collectively WARL, with R=0 W=1 being illegal (#658)
• Delete detailed text surrounding RVC immediates
• Merge branch ‘jscheid-ventana-jscheid/c-pmas’
• Merge pull request #655 from riscv/remove-l-t
• Clarifying FENCE operation behavior for external devices. (#657)
• Merge pull request #652 from rafaelcalcada/master
• Use plural “base ISAs” rather than “base ISA” when appropriate
• Fix capitalization of HINTs
• Fix hyphenation
• Clarify need for HFENCE.GVMA after hgatp.MODE change
• Assin version number 0.1 to Zmmul
• Merge pull request #648 from riscv/zmmul
• Merge pull request #645 from riscv/listofitems
• Merge pull request #644 from EwoutH/patch-1
• marchid request for RudolV (#643)
• Minor mstatus and sstatus layout edits. (#642)
• SUM should be hardwired to 0 for cores without paging (#641)
• Requesting marchid for cv32e40x and cv32e40s (#630)
• marchid request for Ibex (#638)
• Define canonical location of K extension in ISA string
• Clarify hypervisor privilege hierarchy/global interrupt enables
• Add FENCE.TSO and PAUSE to RV32I instruction table
• Clarify that AMOs use the original address when rd == rs1 (#632)
• fix typo in preface
• s/NSE/Custom/ in RVC spec
• wrap long line
• Merge pull request #398 from riscv/pause
• Update preface
• Clarify type of timer interrupt (#617)
• Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778
• Delete duplicate (and now inconsistent) version number given in body text. Closes #618.
• Revert “should -> shall in definition of 0 instruction”
• should -> shall in definition of 0 instruction
• Explain rationale for seting xPP=U on an xRET
• Add preface note that N extension was moved to its own chapter
• Clean up NMI/mepc wording
• Additional FS clarification
• Clarify rm field on widening conversions (#619)
• spell check
• clarify that FS need only be set to dirty if the state is actually changed
• LR/SC extension commentary tweak
• Clarify when FP conversions raise the Inexact flag
• Use consistent wording for FP exception text
• Make unused misa fields 0 (WARL) rather than WLRL. (#615)
• Dedicated section for machine-level memory-mapped registers (not standard CSRs) (#614)
• Clarify G bits in all G-stage PTEs are reserved (#613)
• PMP uses physical addresses (not effective addresses) (#610)
• Update editors
• Update contributors
• mcounteren is WARL
• PMP TOR clarifications
• Another attempt to clarify SEIP RMW semantics
• Attempt to clarify SEIP RMW semantics
• fm=0 for FENCE HINTs
• Both HWBPs and EBREAKs populate mtval (#601)
• marchid request for NEORV32 core (#579)