These registers are only accessible from Debug Mode.

Address	Name	Page
0x7b0	Debug Control and Status (dcsr)
0x7b1	Debug PC (dpc)
0x7b2	Debug Scratch Register 0 (dscratch0)
0x7b3	Debug Scratch Register 1 (dscratch1)

Debug Control and Status (dcsr, at 0x7b0)

[dcsr]

causepriorities are assigned such that the least predictable events have the highest priority.

Field	Description	Access	Reset
[xdebugver] |xdebugver|	0: There is no external debug support. 4: External debug support exists as it is described in this document. 15: There is external debug support, but it does not conform to any available version of this spec.	R	Preset
[ebreakm] |ebreakm|	0: ebreak instructions in M-mode behave as described in the Privileged Spec. 1: ebreak instructions in M-mode enter Debug Mode.	R/W	0
[ebreaks] |ebreaks|	0: ebreak instructions in S-mode behave as described in the Privileged Spec. 1: ebreak instructions in S-mode enter Debug Mode.	R/W	0
[ebreaku] |ebreaku|	0: ebreak instructions in U-mode behave as described in the Privileged Spec. 1: ebreak instructions in U-mode enter Debug Mode.	R/W	0
[stepie] |stepie|	0: Interrupts are disabled during single stepping. 1: Interrupts are enabled during single stepping. Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the debugger. The debugger must not change the value of this bit while the hart is running.	WARL	0
[stopcount] |stopcount|	0: Increment counters as usual. 1: Don’t increment any counters while in Debug Mode or on ebreak instructions that cause entry into Debug Mode. These counters include the cycle and instret CSRs. This is preferred for most debugging scenarios. An implementation may hardwire this bit to 0 or 1.	WARL	Preset
[stoptime] |stoptime|	0: Increment timers as usual. 1: Don’t increment any hart-local timers while in Debug Mode. An implementation may hardwire this bit to 0 or 1.	WARL	Preset
[cause] |cause|	Explains why Debug Mode was entered. When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set causeto the cause with the highest priority. 1: An ebreak instruction was executed. (priority 3) 2: The Trigger Module caused a breakpoint exception. (priority 4, highest) 3: The debugger requested entry to Debug Mode using haltreq. (priority 1) 4: The hart single stepped because stepwas set. (priority 0, lowest) 5: The hart halted directly out of reset due to resethaltreq. It is also acceptable to report 3 when this happens. (priority 2) Other values are reserved for future use.	R	0
[mprven] |mprven|	0: in mstatusis ignored in Debug Mode. 1: in mstatustakes effect in Debug Mode. Implementing this bit is optional. It may be tied to either 0 or 1.	WARL	Preset
[nmip] |nmip|	When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. This is implementation-dependent.	R	0
[step] |step|	When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. The debugger must not change the value of this bit while the hart is running.	R/W	0
[prv] |prv|	Contains the privilege level the hart was operating in when Debug Mode was entered. The encoding is described in Table [tab:privlevel]. A debugger can change this value to change the hart’s privilege level when exiting Debug Mode. Not all privilege levels are supported on all harts. If the encoding written is not supported or the debugger is not allowed to change to it, the hart may change to any supported privilege level.	R/W	3

Debug PC (dpc, at 0x7b1)

[dpc] Upon entry to debug mode, dpcis updated with the virtual address of the next instruction to be executed. The behavior is described in more detail in Table [tab:dpc].

|l|L| Cause & Virtual Address in DPC
ebreak & Address of the ebreak instruction
single step & Address of the instruction that would be executed next if no debugging was going on. Ie. ${\tt pc}+4$ for 32-bit instructions that don’t change program flow, the destination PC on taken jumps/branches, etc.
trigger module & If timingis 0, the address of the instruction which caused the trigger to fire. If timingis 1, the address of the next instruction to be executed at the time that debug mode was entered.
halt request & Address of the next instruction to be executed at the time that debug mode was entered

When resuming, the hart’s PC is updated to the virtual address stored in dpc. A debugger may write dpcto change where the hart resumes.

Debug Scratch Register 0 (dscratch0, at 0x7b2)

[dscratch0] Optional scratch register that can be used by implementations that need it. A debugger must not write to this register unless hartinfo explicitly mentions it (the Debug Module may use this register internally).

Debug Scratch Register 1 (dscratch1, at 0x7b3)

[dscratch1] Optional scratch register that can be used by implementations that need it. A debugger must not write to this register unless hartinfo explicitly mentions it (the Debug Module may use this register internally).